Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedSat Apr 19 11:40:21 2014 product_versionVivado v2013.4 (64-bit)
build_version353583 os_platformLIN64
registration_id208450957_0_0_635 tool_flowVivado
betaFALSE route_designTRUE
target_familyzynq target_devicexc7z010
target_packageclg400 target_speed-1
random_id558ea7d975125ff3af5fef46b8385d55 project_id4a2b4de2c3394aa094a74336e979e4f7
project_iteration1

user_environment
os_nameUbuntu os_releaseUbuntu 12.04.4 LTS
cpu_nameIntel(R) Core(TM) i7 CPU 960 @ 3.20GHz cpu_speed1596.000 MHz
total_processors1 system_ram12.000 GB

vivado_usage
project_data
srcsetcount=0 constraintsetcount=0 designmode=GateLvl prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=[unknown] implstrategy=Vivado Implementation Defaults currentsynthesisrun=[unknown] currentimplrun=impl_1
totalsynthesisruns=0 totalimplruns=1 board=MicroZed Board

unisim_transformation
pre_unisim_transformation
bibuf=130 bufg=2 carry4=127 fdce=257
fdpe=50 fdre=4044 fdse=187 gnd=444
ibuf=15 ibufds=15 iddr=14 lut1=296
lut2=568 lut3=1152 lut4=563 lut5=838
lut6=1298 muxf7=160 muxf8=64 obuf=22
ps7=1 ram32m=2 ram32x1d=1 ramb18e1=1
ramb36e1=46 srl16e=215 srlc32e=94 vcc=229
post_unisim_transformation
bibuf=130 bufg=2 carry4=127 fdce=257
fdpe=50 fdre=4044 fdse=187 gnd=444
ibuf=15 ibufds=15 iddr=14 lut1=296
lut2=568 lut3=1152 lut4=563 lut5=838
lut6=1298 muxf7=160 muxf8=64 obuf=22
ps7=1 ramb18e1=1 ramb36e1=46 ramd32=14
rams32=4 srl16e=215 srlc32e=94 vcc=229

placer
usage
lut=3376 ff=3852 bram36=46 dsp=0
iob=67 bufg=0 global_clocks=1 pll=0
bufr=0 nets=19141 movable_instances=9063 pins=58319
bogomips=6476 effort=2 threads=4 placer_timing_driven=1
timing_constraints_exist=1 placer_runtime=26.610000

power_opt_design
usage
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=3852 srls_augmented=0
srls_newly_gated=0 srls_total=278 bram_ports_augmented=47 bram_ports_newly_gated=0
bram_ports_total=94 flow_state=default
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
IP_Integrator/1
iptotal=1 x_ipvendor=xilinx.com x_iplanguage=VERILOG numblks=28
numreposblks=17 numnonxlnxblks=3 numhierblks=11 maxhierdepth=0
da_axi4_cnt=9 da_board_cnt=4 da_bram_cntlr_cnt=5
axi_bram_ctrl/1
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_bram_ctrl x_ipversion=3.0 x_ipcorerevision=3 x_iplanguage=VERILOG
c_memory_depth=32768 c_family=zynq c_bram_inst_mode=EXTERNAL c_bram_addr_width=15
c_s_axi_addr_width=17 c_s_axi_data_width=32 c_s_axi_id_width=1 c_s_axi_protocol=AXI4
c_s_axi_supports_narrow_burst=0 c_single_port_bram=1 c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32
c_ecc=0 c_ecc_type=0 c_fault_inject=0 c_ecc_onoff_reset_value=0
axi_cdma/1
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_cdma x_ipversion=4.1 x_ipcorerevision=1 x_iplanguage=VERILOG
c_s_axi_lite_addr_width=6 c_s_axi_lite_data_width=32 c_axi_lite_is_async=0 c_m_axi_addr_width=32
c_m_axi_data_width=32 c_m_axi_max_burst_len=16 c_include_dre=0 c_use_datamover_lite=0
c_read_addr_pipe_depth=4 c_write_addr_pipe_depth=4 c_include_sf=0 c_include_sg=0
c_m_axi_sg_addr_width=32 c_m_axi_sg_data_width=32 c_dlytmr_resolution=256 c_family=zynq
axi_crossbar_v2_1_axi_crossbar/1
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=1 x_iplanguage=VERILOG
c_family=zynq c_num_slave_slots=1 c_num_master_slots=2 c_axi_id_width=1
c_axi_addr_width=32 c_axi_data_width=32 c_axi_protocol=0 c_num_addr_ranges=3
c_m_axi_base_addr=0xffffffffffffffffffffffffffffffff00000000c000000000000000fc00000000000000e00000000000000000000000 c_m_axi_addr_width=0x00000000000000000000001100000018000000160000001e c_s_axi_base_id=0x00000000 c_s_axi_thread_id_width=0x00000000
c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1 c_axi_wuser_width=1
c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0xFFFFFFFFFFFFFFFF c_m_axi_read_connectivity=0xFFFFFFFFFFFFFFFF
c_r_register=0 c_s_axi_single_thread=0x00000000 c_s_axi_write_acceptance=0x00000002 c_s_axi_read_acceptance=0x00000002
c_m_axi_write_issuing=0x0000000200000008 c_m_axi_read_issuing=0x0000000200000008 c_s_axi_arb_priority=0x00000000 c_m_axi_secure=0x00000000
c_connectivity_mode=1
axi_crossbar_v2_1_axi_crossbar/2
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=1 x_iplanguage=VERILOG
c_family=zynq c_num_slave_slots=1 c_num_master_slots=3 c_axi_id_width=1
c_axi_addr_width=32 c_axi_data_width=32 c_axi_protocol=2 c_num_addr_ranges=1
c_m_axi_base_addr=0x000000008122000000000000812100000000000081200000 c_m_axi_addr_width=0x000000100000001000000010 c_s_axi_base_id=0x00000000 c_s_axi_thread_id_width=0x00000000
c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1 c_axi_wuser_width=1
c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0x000000010000000100000001 c_m_axi_read_connectivity=0x000000010000000100000001
c_r_register=1 c_s_axi_single_thread=0x00000001 c_s_axi_write_acceptance=0x00000001 c_s_axi_read_acceptance=0x00000001
c_m_axi_write_issuing=0x000000010000000100000001 c_m_axi_read_issuing=0x000000010000000100000001 c_s_axi_arb_priority=0x00000000 c_m_axi_secure=0x000000000000000000000000
c_connectivity_mode=0
axi_gpio/1
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_gpio x_ipversion=2.0 x_ipcorerevision=3 x_iplanguage=VERILOG
c_family=zynq c_s_axi_addr_width=9 c_s_axi_data_width=32 c_gpio_width=1
c_gpio2_width=8 c_all_inputs=0 c_all_inputs_2=1 c_all_outputs=1
c_all_outputs_2=0 c_interrupt_present=0 c_dout_default=0x00000000 c_tri_default=0xFFFFFFFF
c_is_dual=1 c_dout_default_2=0x00000000 c_tri_default_2=0xFFFFFFFF
axi_gpio/2
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_gpio x_ipversion=2.0 x_ipcorerevision=3 x_iplanguage=VERILOG
c_family=zynq c_s_axi_addr_width=9 c_s_axi_data_width=32 c_gpio_width=22
c_gpio2_width=7 c_all_inputs=0 c_all_inputs_2=1 c_all_outputs=1
c_all_outputs_2=0 c_interrupt_present=0 c_dout_default=0x00000000 c_tri_default=0xFFFFFFFF
c_is_dual=1 c_dout_default_2=0x00000000 c_tri_default_2=0xFFFFFFFF
axi_gpio/3
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_gpio x_ipversion=2.0 x_ipcorerevision=3 x_iplanguage=VERILOG
c_family=zynq c_s_axi_addr_width=9 c_s_axi_data_width=32 c_gpio_width=8
c_gpio2_width=1 c_all_inputs=0 c_all_inputs_2=1 c_all_outputs=1
c_all_outputs_2=0 c_interrupt_present=0 c_dout_default=0x00000000 c_tri_default=0xFFFFFFFF
c_is_dual=1 c_dout_default_2=0x00000000 c_tri_default_2=0xFFFFFFFF
axi_protocol_converter_v2_1_axi_protocol_converter/1
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_protocol_converter x_ipversion=2.1 x_ipcorerevision=1 x_iplanguage=VERILOG
c_family=zynq c_m_axi_protocol=2 c_s_axi_protocol=1 c_ignore_id=0
c_axi_id_width=12 c_axi_addr_width=32 c_axi_data_width=32 c_axi_supports_write=1
c_axi_supports_read=1 c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_translation_mode=2
axi_protocol_converter_v2_1_axi_protocol_converter/2
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_protocol_converter x_ipversion=2.1 x_ipcorerevision=1 x_iplanguage=VERILOG
c_family=zynq c_m_axi_protocol=1 c_s_axi_protocol=0 c_ignore_id=1
c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32 c_axi_supports_write=1
c_axi_supports_read=1 c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_translation_mode=2
axi_protocol_converter_v2_1_axi_protocol_converter/3
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_protocol_converter x_ipversion=2.1 x_ipcorerevision=1 x_iplanguage=VERILOG
c_family=zynq c_m_axi_protocol=2 c_s_axi_protocol=1 c_ignore_id=0
c_axi_id_width=12 c_axi_addr_width=32 c_axi_data_width=32 c_axi_supports_write=1
c_axi_supports_read=1 c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_translation_mode=2
blk_mem_gen_v8_1/1
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.1 x_ipcorerevision=0 x_iplanguage=VERILOG
c_family=zynq c_xdevicefamily=zynq c_elaboration_dir=./ c_interface_type=0
c_axi_type=1 c_axi_slave_type=0 c_has_axi_id=0 c_axi_id_width=4
c_mem_type=2 c_byte_size=8 c_algorithm=1 c_prim_type=1
c_load_init_file=0 c_init_file_name=no_coe_file_loaded c_init_file=NONE c_use_default_data=0
c_default_data=0 c_rst_type=SYNC c_has_rsta=1 c_rst_priority_a=CE
c_rstram_a=0 c_inita_val=0 c_has_ena=1 c_has_regcea=0
c_use_byte_wea=1 c_wea_width=4 c_write_mode_a=WRITE_FIRST c_write_width_a=32
c_read_width_a=32 c_write_depth_a=32768 c_read_depth_a=32768 c_addra_width=32
c_has_rstb=1 c_rst_priority_b=CE c_rstram_b=0 c_initb_val=0
c_has_enb=1 c_has_regceb=0 c_use_byte_web=1 c_web_width=4
c_write_mode_b=WRITE_FIRST c_write_width_b=32 c_read_width_b=32 c_write_depth_b=32768
c_read_depth_b=32768 c_addrb_width=32 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0
c_has_mux_output_regs_a=0 c_has_mux_output_regs_b=0 c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0
c_has_softecc_output_regs_b=0 c_use_softecc=0 c_use_ecc=0 c_has_injecterr=0
c_sim_collision_check=ALL c_common_clk=0 c_enable_32bit_address=1 c_disable_warn_bhv_coll=0
c_disable_warn_bhv_range=0 c_use_bram_block=1 c_ctrl_ecc_algo=NONE
fifo_generator_v11_0/1
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=fifo_generator x_ipversion=11.0 x_ipcorerevision=1 x_iplanguage=VERILOG
c_common_clock=0 c_count_type=0 c_data_count_width=14 c_default_value=BlankString
c_din_width=32 c_dout_rst_val=0 c_dout_width=32 c_enable_rlocs=0
c_family=zynq c_full_flags_rst_val=1 c_has_almost_empty=0 c_has_almost_full=0
c_has_backup=0 c_has_data_count=0 c_has_int_clk=0 c_has_meminit_file=0
c_has_overflow=0 c_has_rd_data_count=0 c_has_rd_rst=0 c_has_rst=1
c_has_srst=0 c_has_underflow=0 c_has_valid=0 c_has_wr_ack=0
c_has_wr_data_count=0 c_has_wr_rst=0 c_implementation_type=2 c_init_wr_pntr_val=0
c_memory_type=1 c_mif_file_name=BlankString c_optimization_mode=0 c_overflow_low=0
c_preload_latency=1 c_preload_regs=0 c_prim_fifo_type=8kx4 c_prog_empty_thresh_assert_val=2
c_prog_empty_thresh_negate_val=3 c_prog_empty_type=0 c_prog_full_thresh_assert_val=16381 c_prog_full_thresh_negate_val=16380
c_prog_full_type=0 c_rd_data_count_width=14 c_rd_depth=16384 c_rd_freq=1
c_rd_pntr_width=14 c_underflow_low=0 c_use_dout_rst=1 c_use_ecc=0
c_use_embedded_reg=0 c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_valid_low=0
c_wr_ack_low=0 c_wr_data_count_width=14 c_wr_depth=16384 c_wr_freq=1
c_wr_pntr_width=14 c_wr_response_latency=1 c_msgon_val=1 c_enable_rst_sync=1
c_error_injection_type=0 c_synchronizer_stage=2 c_interface_type=0 c_axi_type=1
c_has_axi_wr_channel=1 c_has_axi_rd_channel=1 c_has_slave_ce=0 c_has_master_ce=0
c_add_ngc_constraint=0 c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0
c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=64 c_has_axi_awuser=0
c_has_axi_wuser=0 c_has_axi_buser=0 c_has_axi_aruser=0 c_has_axi_ruser=0
c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_wuser_width=1 c_axi_buser_width=1
c_axi_ruser_width=1 c_has_axi_id=0 c_has_axis_tdata=1 c_has_axis_tid=0
c_has_axis_tdest=0 c_has_axis_tuser=1 c_has_axis_tready=1 c_has_axis_tlast=0
c_has_axis_tstrb=0 c_has_axis_tkeep=0 c_axis_tdata_width=8 c_axis_tid_width=1
c_axis_tdest_width=1 c_axis_tuser_width=4 c_axis_tstrb_width=1 c_axis_tkeep_width=1
c_wach_type=0 c_wdch_type=0 c_wrch_type=0 c_rach_type=0
c_rdch_type=0 c_axis_type=0 c_implementation_type_wach=1 c_implementation_type_wdch=1
c_implementation_type_wrch=1 c_implementation_type_rach=1 c_implementation_type_rdch=1 c_implementation_type_axis=1
c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0 c_application_type_rach=0
c_application_type_rdch=0 c_application_type_axis=0 c_prim_fifo_type_wach=512x36 c_prim_fifo_type_wdch=1kx36
c_prim_fifo_type_wrch=512x36 c_prim_fifo_type_rach=512x36 c_prim_fifo_type_rdch=1kx36 c_prim_fifo_type_axis=1kx18
c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0 c_use_ecc_rach=0
c_use_ecc_rdch=0 c_use_ecc_axis=0 c_error_injection_type_wach=0 c_error_injection_type_wdch=0
c_error_injection_type_wrch=0 c_error_injection_type_rach=0 c_error_injection_type_rdch=0 c_error_injection_type_axis=0
c_din_width_wach=32 c_din_width_wdch=64 c_din_width_wrch=2 c_din_width_rach=32
c_din_width_rdch=64 c_din_width_axis=1 c_wr_depth_wach=16 c_wr_depth_wdch=1024
c_wr_depth_wrch=16 c_wr_depth_rach=16 c_wr_depth_rdch=1024 c_wr_depth_axis=1024
c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4 c_wr_pntr_width_rach=4
c_wr_pntr_width_rdch=10 c_wr_pntr_width_axis=10 c_has_data_counts_wach=0 c_has_data_counts_wdch=0
c_has_data_counts_wrch=0 c_has_data_counts_rach=0 c_has_data_counts_rdch=0 c_has_data_counts_axis=0
c_has_prog_flags_wach=0 c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0 c_has_prog_flags_rach=0
c_has_prog_flags_rdch=0 c_has_prog_flags_axis=0 c_prog_full_type_wach=0 c_prog_full_type_wdch=0
c_prog_full_type_wrch=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0 c_prog_full_type_axis=0
c_prog_full_thresh_assert_val_wach=1023 c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023 c_prog_full_thresh_assert_val_rach=1023
c_prog_full_thresh_assert_val_rdch=1023 c_prog_full_thresh_assert_val_axis=1023 c_prog_empty_type_wach=0 c_prog_empty_type_wdch=0
c_prog_empty_type_wrch=0 c_prog_empty_type_rach=0 c_prog_empty_type_rdch=0 c_prog_empty_type_axis=0
c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022 c_prog_empty_thresh_assert_val_rach=1022
c_prog_empty_thresh_assert_val_rdch=1022 c_prog_empty_thresh_assert_val_axis=1022 c_reg_slice_mode_wach=0 c_reg_slice_mode_wdch=0
c_reg_slice_mode_wrch=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0 c_reg_slice_mode_axis=0
c_axi_len_width=8 c_axi_lock_width=1
proc_sys_reset/1
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=proc_sys_reset x_ipversion=5.0 x_ipcorerevision=3 x_iplanguage=VERILOG
c_family=zynq c_ext_rst_width=4 c_aux_rst_width=4 c_ext_reset_high=0
c_aux_reset_high=0 c_num_bus_rst=1 c_num_perp_rst=1 c_num_interconnect_aresetn=1
c_num_perp_aresetn=1
processing_system7_v5_3_processing_system7/1
iptotal=1 x_ipproduct=Vivado 2013.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=processing_system7 x_ipversion=5.3 x_ipcorerevision=1 x_iplanguage=VERILOG
c_en_emio_enet0=0 c_en_emio_enet1=0 c_en_emio_trace=0 c_include_trace_buffer=0
c_trace_buffer_fifo_size=128 use_trace_data_edge_detector=0 c_trace_buffer_clock_delay=12 c_emio_gpio_width=64
c_include_acp_trans_check=0 c_use_default_acp_user_val=0 c_s_axi_acp_aruser_val=31 c_s_axi_acp_awuser_val=31
c_m_axi_gp0_id_width=12 c_m_axi_gp0_enable_static_remap=0 c_m_axi_gp1_id_width=12 c_m_axi_gp1_enable_static_remap=0
c_s_axi_gp0_id_width=6 c_s_axi_gp1_id_width=6 c_s_axi_acp_id_width=3 c_s_axi_hp0_id_width=6
c_s_axi_hp0_data_width=64 c_s_axi_hp1_id_width=6 c_s_axi_hp1_data_width=64 c_s_axi_hp2_id_width=6
c_s_axi_hp2_data_width=64 c_s_axi_hp3_id_width=6 c_s_axi_hp3_data_width=64 c_m_axi_gp0_thread_id_width=12
c_m_axi_gp1_thread_id_width=12 c_num_f2p_intr_inputs=1 c_dq_width=32 c_dqs_width=4
c_dm_width=4 c_mio_primitive=54 c_ps7_si_rev=PRODUCTION c_fclk_clk0_buf=true
c_fclk_clk1_buf=true c_fclk_clk2_buf=false c_fclk_clk3_buf=false c_package_name=clg400

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=zynq
die=xc7z010clg400-1 package=clg400 speedgrade=-1 version=2013.4
platform=lin64 temp_grade=commercial process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=100 pct_inputs_defined=3 user_junc_temp=42.7 (C)
ambient_temp=25.0 (C) user_effective_thetaja=11.533192 airflow=250 (LFM) heatsink=none
user_thetasa=0.0 (C/W) board_selection=medium (10"x10") board_layers=8to11 (8 to 11 Layers) user_thetajb=9.3 (C/W)
user_board_temp=25.0 (C) junction_temp=42.7 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 on-chip_power=1.535135 dynamic=1.408228
effective_thetaja=11.5 thetasa=0.0 (C/W) thetajb=9.3 (C/W) off-chip_power=0.120750
clocks=0.027733 logic=0.004691 signals=0.010459 bram=0.007465
i/o=0.049599 ps7=1.308281 devstatic=0.126908 vccint_voltage=1.000000
vccint_total_current=0.062683 vccint_dynamic_current=0.055562 vccint_static_current=0.007121 vccaux_voltage=1.800000
vccaux_total_current=0.035846 vccaux_dynamic_current=0.024234 vccaux_static_current=0.011613 vcco33_voltage=3.300000
vcco33_total_current=0.000000 vcco33_dynamic_current=0.000000 vcco33_static_current=0.000000 vcco25_voltage=2.500000
vcco25_total_current=0.001076 vcco25_dynamic_current=0.000076 vcco25_static_current=0.001000 vcco18_voltage=1.800000
vcco18_total_current=0.000000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco15_voltage=1.500000
vcco15_total_current=0.000000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco135_voltage=1.350000
vcco135_total_current=0.000000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco12_voltage=1.200000
vcco12_total_current=0.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vccaux_io_voltage=1.800000
vccaux_io_total_current=0.000000 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccbram_voltage=1.000000
vccbram_total_current=0.001983 vccbram_dynamic_current=0.000573 vccbram_static_current=0.001409 mgtavcc_voltage=1.000000
mgtavcc_total_current=0.000000 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavtt_voltage=1.200000
mgtavtt_total_current=0.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtvccaux_voltage=1.800000
mgtvccaux_total_current=0.000000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000 vccpint_voltage=1.000000
vccpint_total_current=0.419271 vccpint_dynamic_current=0.390891 vccpint_static_current=0.028380 vccpaux_voltage=1.800000
vccpaux_total_current=0.044720 vccpaux_dynamic_current=0.034390 vccpaux_static_current=0.010330 vccpll_voltage=1.800000
vccpll_total_current=0.116000 vccpll_dynamic_current=0.113000 vccpll_static_current=0.003000 vcco_ddr_voltage=1.500000
vcco_ddr_total_current=0.510750 vcco_ddr_dynamic_current=0.508750 vcco_ddr_static_current=0.002000 vcco_mio0_voltage=1.800000
vcco_mio0_total_current=0.004208 vcco_mio0_dynamic_current=0.003208 vcco_mio0_static_current=0.001000 vcco_mio1_voltage=1.800000
vcco_mio1_total_current=0.003187 vcco_mio1_dynamic_current=0.002187 vcco_mio1_static_current=0.001000 vccadc_voltage=1.800000
vccadc_total_current=0.020000 vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 confidence_level_design_state=High
confidence_level_clock_activity=High confidence_level_io_activity=Low confidence_level_internal_activity=Medium confidence_level_device_models=High
confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=3299 slice_luts_loced=0 slice_luts_available=17600 slice_luts_util_percentage=18.74
lut_as_logic_used=3077 lut_as_logic_loced=0 lut_as_logic_available=17600 lut_as_logic_util_percentage=17.48
lut_as_memory_used=222 lut_as_memory_loced=0 lut_as_memory_available=6000 lut_as_memory_util_percentage=3.70
lut_as_distributed_ram_used=10 lut_as_distributed_ram_loced=0 lut_as_shift_register_used=212 lut_as_shift_register_loced=0
slice_registers_used=3852 slice_registers_loced=0 slice_registers_available=35200 slice_registers_util_percentage=10.94
register_as_flip_flop_used=3852 register_as_flip_flop_loced=0 register_as_flip_flop_available=35200 register_as_flip_flop_util_percentage=10.94
register_as_latch_used=0 register_as_latch_loced=0 register_as_latch_available=35200 register_as_latch_util_percentage=0.00
f7_muxes_used=87 f7_muxes_loced=0 f7_muxes_available=8800 f7_muxes_util_percentage=0.98
f8_muxes_used=32 f8_muxes_loced=0 f8_muxes_available=4400 f8_muxes_util_percentage=0.72
slice_used=1448 slice_loced=0 slice_available=4400 slice_util_percentage=32.90
lut_as_logic_used=3077 lut_as_logic_loced=0 lut_as_logic_available=17600 lut_as_logic_util_percentage=17.48
using_o5_output_only_used=0 using_o5_output_only_loced= using_o6_output_only_used=2311 using_o6_output_only_loced=
using_o5_and_o6_used=766 using_o5_and_o6_loced= lut_as_memory_used=222 lut_as_memory_loced=0
lut_as_memory_available=6000 lut_as_memory_util_percentage=3.70 lut_as_distributed_ram_used=10 lut_as_distributed_ram_loced=0
using_o5_output_only_used=0 using_o5_output_only_loced= using_o6_output_only_used=2 using_o6_output_only_loced=
using_o5_and_o6_used=8 using_o5_and_o6_loced= lut_as_shift_register_used=212 lut_as_shift_register_loced=0
using_o5_output_only_used=10 using_o5_output_only_loced= using_o6_output_only_used=136 using_o6_output_only_loced=
using_o5_and_o6_used=66 using_o5_and_o6_loced= lut_flip_flop_pairs_used=4201 lut_flip_flop_pairs_loced=0
lut_flip_flop_pairs_available=17600 lut_flip_flop_pairs_util_percentage=23.86 fully_used_lut_ff_pairs_used=2166 fully_used_lut_ff_pairs_loced=
lut_ff_pairs_with_unused_lut_used=912 lut_ff_pairs_with_unused_lut_loced= lut_ff_pairs_with_unused_flip_flop_used=1123 lut_ff_pairs_with_unused_flip_flop_loced=
unique_control_sets_used=192 minimum_number_of_registers_lost_to_control_set_restriction_used=484(Lost)
memory
block_ram_tile_used=46.5 block_ram_tile_loced=0 block_ram_tile_available=60 block_ram_tile_util_percentage=76.66
ramb36_fifo*_used=46 ramb36_fifo*_loced=0 ramb36_fifo*_available=60 ramb36_fifo*_util_percentage=76.66
ramb36e1_only_used=46 ramb18_used=1 ramb18_loced=0 ramb18_available=120
ramb18_util_percentage=0.83 ramb18e1_only_used=1
dsp
dsps_used=0 dsps_loced=0 dsps_available=80 dsps_util_percentage=0.00
io_and_gtx
bonded_iob_used=67 bonded_iob_loced=67 bonded_iob_available=100 bonded_iob_util_percentage=67.00
iob_master_pads_used=37 iob_master_pads_loced= iob_slave_pads_used=30 iob_slave_pads_loced=
bonded_ipads_used=0 bonded_ipads_loced=0 bonded_ipads_available=2 bonded_ipads_util_percentage=0.00
bonded_iopads_used=130 bonded_iopads_loced=130 bonded_iopads_available=130 bonded_iopads_util_percentage=100.00
ibufgds_used=0 ibufgds_loced=0 ibufgds_available=96 ibufgds_util_percentage=0.00
idelayctrl_used=0 idelayctrl_loced=0 idelayctrl_available=2 idelayctrl_util_percentage=0.00
in_fifo_used=0 in_fifo_loced=0 in_fifo_available=8 in_fifo_util_percentage=0.00
out_fifo_used=0 out_fifo_loced=0 out_fifo_available=8 out_fifo_util_percentage=0.00
phaser_ref_used=0 phaser_ref_loced=0 phaser_ref_available=2 phaser_ref_util_percentage=0.00
phy_control_used=0 phy_control_loced=0 phy_control_available=2 phy_control_util_percentage=0.00
phaser_out_phaser_out_phy_used=0 phaser_out_phaser_out_phy_loced=0 phaser_out_phaser_out_phy_available=8 phaser_out_phaser_out_phy_util_percentage=0.00
phaser_in_phaser_in_phy_used=0 phaser_in_phaser_in_phy_loced=0 phaser_in_phaser_in_phy_available=8 phaser_in_phaser_in_phy_util_percentage=0.00
idelaye2_idelaye2_finedelay_used=0 idelaye2_idelaye2_finedelay_loced=0 idelaye2_idelaye2_finedelay_available=100 idelaye2_idelaye2_finedelay_util_percentage=0.00
odelaye2_odelaye2_finedelay_used=0 odelaye2_odelaye2_finedelay_loced=0 odelaye2_odelaye2_finedelay_available=0 odelaye2_odelaye2_finedelay_util_percentage=0.00
ibufds_gte2_used=0 ibufds_gte2_loced=0 ibufds_gte2_available=0 ibufds_gte2_util_percentage=0.00
ilogic_used=14 ilogic_loced=14 ilogic_available=100 ilogic_util_percentage=14.00
iff_iddr_register_used=14 iff_iddr_register_loced=14 ologic_used=0 ologic_loced=0
ologic_available=100 ologic_util_percentage=0.00
clocking
bufgctrl_used=1 bufgctrl_loced=0 bufgctrl_available=32 bufgctrl_util_percentage=3.12
bufio_used=0 bufio_loced=0 bufio_available=8 bufio_util_percentage=0.00
mmcme2_adv_used=0 mmcme2_adv_loced=0 mmcme2_adv_available=2 mmcme2_adv_util_percentage=0.00
plle2_adv_used=0 plle2_adv_loced=0 plle2_adv_available=2 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_loced=0 bufmrce_available=4 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_loced=0 bufhce_available=48 bufhce_util_percentage=0.00
bufr_used=0 bufr_loced=0 bufr_available=8 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_loced=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_loced=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_loced=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_loced=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_loced=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_loced=0 icape2_available=2 icape2_util_percentage=0.00
startupe2_used=0 startupe2_loced=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_loced=0 xadc_available=1 xadc_util_percentage=0.00
primitives
fdre_used=3359 lut3_used=1070 lut6_used=806 lut5_used=684
lut4_used=627 lut2_used=560 fdce_used=256 fdse_used=187
srl16e_used=184 bibuf_used=130 carry4_used=120 lut1_used=96
srlc32e_used=94 muxf7_used=87 fdpe_used=50 ramb36e1_used=46
muxf8_used=32 obuf_used=22 ibufds_used=15 ibuf_used=15
ramd32_used=14 iddr_used=14 rams32_used=4 ramb18e1_used=1
ps7_used=1 bufg_used=1
io_standard
diff_sstl135_r=0 sstl18_ii=0 lvcmos15=0 diff_hstl_i=0
lvds_25=1 diff_sstl15_r=0 lvttl=0 hstl_ii=0
diff_mobile_ddr=0 pci33_3=0 diff_sstl18_ii=0 sstl135=0
lvcmos25=1 sstl135_r=0 diff_hstl_ii_18=0 hstl_ii_18=0
mini_lvds_25=0 sstl15=1 lvcmos12=0 diff_hstl_ii=0
rsds_25=0 diff_sstl135=0 sstl18_i=0 lvcmos18=1
mobile_ddr=0 blvds_25=0 diff_sstl15=1 lvcmos33=1
hstl_i=0 diff_sstl18_i=0 ppds_25=0 diff_hsul_12=0
sstl15_r=0 hsul_12=0 diff_hstl_i_18=0 hstl_i_18=0
tmds_33=0

router
usage
lut=3588 ff=3852 bram36=46 dsp=0
iob=67 bufg=0 global_clocks=1 pll=0
bufr=0 nets=19094 movable_instances=9016 pins=58272
bogomips=6476 high_fanout_nets=2 effort=2 threads=4
router_timing_driven=1 timing_constraints_exist=1 congestion_level=0 router_runtime=20.400000