ethernet_mac_tst Project Status (11/26/2012 - 15:59:32) | |||
Project File: | Phase2.xise | Parser Errors: | No Errors |
Module Name: | ethernet_mac_tst | Implementation State: | Synthesized |
Target Device: | xc6slx9-3tqg144 |
|
|
Product Version: | ISE 13.3 |
|
|
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: |
|
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Out of Date | Mon Nov 26 15:41:23 2012 | |
WebTalk Log File | Out of Date | Mon Nov 26 15:41:24 2012 |