ethernet_mac_tst Project Status (11/26/2012 - 15:59:32)
Project File: Phase2.xise Parser Errors: No Errors
Module Name: ethernet_mac_tst Implementation State: Synthesized
Target Device: xc6slx9-3tqg144
  • Errors:
 
Product Version:ISE 13.3
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateMon Nov 26 15:41:23 2012
WebTalk Log FileOut of DateMon Nov 26 15:41:24 2012

Date Generated: 11/26/2012 - 16:17:27