top_module Project Status (06/14/2013 - 11:11:38) | |||
Project File: | Phase2.xise | Parser Errors: | No Errors |
Module Name: | top_module | Implementation State: | Programming File Generated |
Target Device: | xc6slx9-3tqg144 |
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No Errors |
Product Version: | ISE 13.3 |
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395 Warnings (0 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [+] |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Fri Jun 14 11:09:17 2013 | 0 | 355 Warnings (0 new) | 47 Infos (0 new) | |
Translation Report | Current | Fri Jun 14 11:09:26 2013 | 0 | 1 Warning (0 new) | 8 Infos (0 new) | |
Map Report | Current | Fri Jun 14 11:10:32 2013 | 0 | 12 Warnings (0 new) | 8 Infos (0 new) | |
Place and Route Report | Current | Fri Jun 14 11:11:13 2013 | 0 | 16 Warnings (0 new) | 0 | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Fri Jun 14 11:11:23 2013 | 0 | 0 | 2 Infos (0 new) | |
Bitgen Report | Current | Fri Jun 14 11:11:37 2013 | 0 | 11 Warnings (0 new) | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Thu Jun 13 15:00:41 2013 | |
WebTalk Report | Current | Fri Jun 14 11:11:38 2013 | |
WebTalk Log File | Current | Fri Jun 14 11:11:38 2013 |