top_module Project Status (06/14/2013 - 11:11:38)
Project File: Phase2.xise Parser Errors: No Errors
Module Name: top_module Implementation State: Programming File Generated
Target Device: xc6slx9-3tqg144
  • Errors:
No Errors
Product Version:ISE 13.3
  • Warnings:
395 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [+]
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Jun 14 11:09:17 20130355 Warnings (0 new)47 Infos (0 new)
Translation ReportCurrentFri Jun 14 11:09:26 201301 Warning (0 new)8 Infos (0 new)
Map ReportCurrentFri Jun 14 11:10:32 2013012 Warnings (0 new)8 Infos (0 new)
Place and Route ReportCurrentFri Jun 14 11:11:13 2013016 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrentFri Jun 14 11:11:23 2013002 Infos (0 new)
Bitgen ReportCurrentFri Jun 14 11:11:37 2013011 Warnings (0 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateThu Jun 13 15:00:41 2013
WebTalk ReportCurrentFri Jun 14 11:11:38 2013
WebTalk Log FileCurrentFri Jun 14 11:11:38 2013

Date Generated: 06/14/2013 - 11:11:38