top_module Project Status (05/13/2013 - 14:15:44)
Project File: Phase2.xise Parser Errors: No Errors
Module Name: top_module Implementation State: Programming File Generated
Target Device: xc6slx9-3tqg144
  • Errors:
No Errors
Product Version:ISE 13.3
  • Warnings:
496 Warnings (458 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 1,574 11,440 13%  
    Number used as Flip Flops 1,571      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 3      
Number of Slice LUTs 2,109 5,720 36%  
    Number used as logic 2,019 5,720 35%  
        Number using O6 output only 1,352      
        Number using O5 output only 230      
        Number using O5 and O6 437      
        Number used as ROM 0      
    Number used as Memory 38 1,440 2%  
        Number used as Dual Port RAM 24      
            Number using O6 output only 0      
            Number using O5 output only 4      
            Number using O5 and O6 20      
        Number used as Single Port RAM 7      
            Number using O6 output only 3      
            Number using O5 output only 0      
            Number using O5 and O6 4      
        Number used as Shift Register 7      
            Number using O6 output only 7      
            Number using O5 output only 0      
            Number using O5 and O6 0      
    Number used exclusively as route-thrus 52      
        Number with same-slice register load 29      
        Number with same-slice carry load 23      
        Number with other load 0      
Number of occupied Slices 794 1,430 55%  
Nummber of MUXCYs used 568 2,860 19%  
Number of LUT Flip Flop pairs used 2,406      
    Number with an unused Flip Flop 993 2,406 41%  
    Number with an unused LUT 297 2,406 12%  
    Number of fully used LUT-FF pairs 1,116 2,406 46%  
    Number of unique control sets 136      
    Number of slice register sites lost
        to control set restrictions
431 11,440 3%  
Number of bonded IOBs 74 102 72%  
    Number of LOCed IOBs 74 74 100%  
    IOB Flip Flops 2      
    IOB Master Pads 2      
    IOB Slave Pads 2      
Number of RAMB16BWERs 10 32 31%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 3 32 9%  
    Number used as BUFIO2s 3      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 9 16 56%  
    Number used as BUFGs 9      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 1 200 1%  
    Number used as ILOGIC2s 1      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 1 200 1%  
    Number used as OLOGIC2s 1      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.64      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon May 13 14:14:27 20130458 Warnings (458 new)40 Infos (40 new)
Translation ReportCurrentMon May 13 14:14:35 2013007 Infos (0 new)
Map ReportCurrentMon May 13 14:15:02 2013014 Warnings (0 new)8 Infos (0 new)
Place and Route ReportCurrentMon May 13 14:15:25 2013013 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrentMon May 13 14:15:31 2013002 Infos (0 new)
Bitgen ReportCurrentMon May 13 14:15:42 2013011 Warnings (0 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateFri May 10 16:26:26 2013
WebTalk ReportCurrentMon May 13 14:15:43 2013
WebTalk Log FileCurrentMon May 13 14:15:44 2013

Date Generated: 05/13/2013 - 14:15:44