Changes between Version 4 and Version 5 of ZyboDemo
- Timestamp:
- Mar 3, 2017, 1:01:21 PM (7 years ago)
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ZyboDemo
v4 v5 7 7 * Vivado 2015.4 with SDK 8 8 * Xilinx Petalinux 2015.4 9 10 Source --11 12 settings64.sh from vivado install directory13 14 settings.sh from petalinux install directory15 16 -> Ignore error about tftp server17 18 '''DO NOT SOURCE THESE IN THE SAME CONSOLE AT THE SAME TIME. IT WILL BREAK THINGS.'''19 9 20 10 == Required Downloads … … 28 18 == Hardware Design 29 19 20 Source settings64.sh from {Vivado Install Directory}.\\ 30 21 In Vivado, create a new project.\\ 31 22 Choose for it to be an RTL project, and don't add any sources now.\\ 32 23 When selecting your default part, choose `Boards` at the top, and select Zybo (This won't be here if you haven't installed the Zybo Board file yet)\\\\ 33 Navigate to `Create Block Design` on the left .\\24 Navigate to `Create Block Design` on the left, name the hardware "system".\\ 34 25 From here you can add anything you need on your project. I chose to add a ZNYQ7 Processor and three GPIO ports.\\ 35 26 Once you're done, run `Block Automation` on the top.\\ … … 38 29 >>Run `Connection Automation` again, and connect the GPIO to btns, leds, and sws.\\ 39 30 Run `Refresh Connections` and then `Validate Design`.\\\\ 31 Navigate to `Project Manager` on the left.\\ 32 Right click on `system` in `Design Sources` and `Create HDL Wrapper`.\\ 33 Click on `Generate Bitsream` on the bottom left.\\ 34 Go to `File -> Export -> Export Hardware`. Choose to include the bitstream.\\ 40 35 36 == Embedded Linux through [http://www.wiki.xilinx.com/PetaLinux PetaLinux] 41 37 42 Hardware Design -- 43 44 Open Vivado,[[BR]] 45 Create new RTL project,[[BR]] 46 Don't add sources or constraints or IPs,[[BR]] 47 Select ZYBO for default part,[[BR]] 48 49 In new project Create Block Design,[[BR]] 50 Add ZYNQ7 Processing and Three GPIO ports,[[BR]] 51 Run Block Automation,[[BR]] 52 Run Connection Automation, select S_AXI connections,[[BR]] 53 Run Connection Automation again, connect gpio_0 to btns, gpio_1 to leds, gpio_2 to sws,[[BR]] 54 Refresh Connections and Validate Design,[[BR]] 55 56 Click on project manager,[[BR]] 57 Right click system under Design Sources and Create HDL Wrapper,[[BR]] 58 Generate Bitstream,[[BR]] 59 Go to File->Export->Export Hardware, include bitstream[[BR]] 60 61 62 Embedded Linux -- 63 64 Create petalinux project : petalinux-create --type project --name zybo_linux --source ~/Desktop/Digilent-Zybo-Linux-BD-v2015.4.bsp [[BR]] 65 Config petalinux project : petalinux-config --get-hw-description zybo_spi/zybo_spi.sdk --project zybo_linux (Replace zybo_spi with name of project and make sure you're pointing to the right place)[[BR]] 66 Enable dropbear SSH : petalinux-config -c rootfs --project zybo_linux, FileSystem Packages->Console/Network->dropbear 67 Build the image : petalinux-build --project zybo_linux/ 68 38 In a new terminal, source settings.sh from {Petalinux Install Directory}.\\ 39 Create the petalinux project : {{{petalinux-create --type project --name {project name} --source {path/to/Zybo Board Support file (should be a BSP file)}}}}\\ 40 Configure the project : {{{petalinux-config --get-hw-description {path/to/Vivado Project}/project.sdk (ex. ~/Documents/projects/zybo/zybo.sdk)}}}\\ 41 Enable Dropbear SSH : {{{petalinux-config -c rootfs --project {path/to/petalinux project)}}} and navigate to `FileSystem Packages -> Console/Network -> dropbear`.\\ 42 Build the image : {{{petalinux-build --project {path/to/petalinux project}}}}\\ 69 43 70 44 Create FSBL -- (Currently having problems with this one) … … 75 49 Copy BOOT.bin and zybo_linux/images/linux/image.ub to SD card,[[BR]] 76 50 SD card must be formatted so that the first 4MiB are unallocated, the next partition is at least 100MiB and is fat32, and the remainder is ex4 51 52 53 == General Notes 54 55 * Don't have petalinux and vivado sourced in the same terminal at the same time unless you're using the petalinux-package commands. It will just cause errors and extra headache. 56 * Make sure that your project's target language in Vivado is set VHDL and not Verilog. 57 *