wiki:Z80Laptop

Version 42 (modified by Eric Hazen, 4 years ago) (diff)

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Dreaming of a CP/M Z80 laptop!

Evolution from calculator CPU

  • 512Kx8 SRAM with bank switching (including EEPROM)
  • Interrupt support
  • Add some hardware serial ports (maybe 2)
  • Add 2X SD card interfaces
  • PIO or at least an expansion bus

Evolving Design

  • Z80 CPU, DART, PIO
  • AT28C256 32Kx8 EEPROM
  • AS6C4008 512Kx8 SRAM
  • Clocks: 8MHz osc /2 => 4MHz CPU clock
  • Clocks: 1.8432MHz / 12 => 16X 9600 clock
  • MAX232 or equiv; DB-25 for RS-232

Useful Tools

Video / Keyboard?

Maybe a ​Basys 3? There is even a ​demo project which includes mouse and VGA support (not that we need the mouse!)

The XC7A35T has 100 BRAMs (each 512x36) so enough for several bits per pixel at 640x480.

Maybe CMOD S7: ​https://store.digilentinc.com/cmod-s7-breadboardable-spartan-7-fpga-module/

VGA modes (60Hz) (from ​blog

Mode Pixels Clock RAM Adx (256 color)
640x480 370k 25.175 MHz 18
800x600 480k 40.000 MHz 18
1024x720 922k 74.250 MHz 20
1920x1080 2.1M 148.500 MHz 21

For some sort of DIY video with an FPGA or even TTL logic, for 640x480 we need about 10 bits of row count (525 lines) and 10 bits of pixel count (800 total clocks). Active area is 10 bits horiz and 9 bits vertical.

IMSG171 is a classic RAMDAC good for VGA output (and still available on eBay). 

VGA timing (640x480 60Hz):
    horiz:  16 + 96 + 48 + 640 = 800 at 25.2 MHz
    vert:   11 + 2 + 31 + 480 = 524

Horiz line 800 pixels, 100 bytes
Various 8x16 fonts from IMB seem reasonable

For just bit-mapped graphics, need 100 x 480 = 48k RAM
Hardware character generator seems a good option.

Horizontal logic:

  Front porch:   2 byte times
  Horiz sync:   12 byte times
  Back porch:    6 byte times
  Horiz active: 80 byte times

  Most convenient is probably to start at 0 with first active

Vertical logic:

  480 lines (30 character frames of 16 lines each)
  44 lines of sync:
    VFP:  11 lines
    VS:    2 lines
    VBP:  31 lines

Other

Lots of NVRAM / flash and RAM disk

Parts:

  • 128Kx8 flash: GLS29EE010-70-4C-PHE
  • 32Kx8 flash: AT28C256-15PU
  • 512Kx8 SRAM: AS6C4008-55PCN
  • 128Kx8 SRAM: AS6C1008-55PCN
  • Z80 8MHz CPU: Z84C0008PEG
  • Serial I/O:
    • SCN2661 / SCN 68661 EPCI (single port w/ baud rate gen)
    • SCN68681 or SCC2681 (progr. baud rate, avail on eBay)
    • Z80 DART: Z8470 (needs baud rate) or SIO same deal

Floppy controllers:

  • FD1797 (needs data separator) ​sample schem
  • WD2797 (on-chip PLL data separator)
  • WD37C65C (NEC 765 clone?)
  • FDC9266
  • WD1770/1771/1772 (5-1/4 inch drives only?)

SDCard interfaces:

IDE interfaces:

Thinking about making an Osh Park test board with WD2797 and 8" and 5" floppy connectors. Could have an ATMega or Xilix eval board interface. Possibly RC2014 compliant, need to study their bus.

Software:

  • ​FDU disk utility supports amongst other things formatting of 8" floppies

Emulators:

Design ideas:

  • In 13x9 inch box, keyboard and PCB ~ 12 x 2.8 would fit.
  • Need a terminal emulator to generate VGA timing and deal with USB/PS-2 keyboard.