Changes between Initial Version and Version 1 of Xilinx_Ethernet


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Timestamp:
Nov 8, 2013, 10:17:54 AM (6 years ago)
Author:
hazen
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  • Xilinx_Ethernet

    v1 v1  
     1This page contains design notes on logic implementation
     2of TCP/IP protocols.
     3
     4
     5== TCP/IP in Logic ==
     6
     7Jeremy Mans "IPBUS"
     8
     9* [http://ohm.bu.edu/%7Ehazen/CMS/IPBUS_spec_v1_1.pdf Spec]
     10* [http://ehazen.web.cern.ch/ehazen/exch/ipbus_12Apr10.zip ipbus_12Apr10.zip]
     11* [http://cms1.bu.edu/~hazen/hcalUpgrade/ Upgrade Software]
     12''''TriDAS/hcal/hcalUpgrade/src/common/RequestResponse.cc''' and
     13''''TriDAS/hcal/hcalUpgrade/include/hcal/upgrade/IPbusCore.hh''' for Jeremy's library in C++.
     14== VHDL version of IPBUS for Spartan 6 chips ==
     15* [http://ohm.bu.edu/~cdubois/Ethernet/slow_version.tar.gz old source files]
     16* [http://ohm.bu.edu/~cdubois/Ethernet/faster_version.tar.gz new source files]
     17* [http://ohm.bu.edu/~cdubois/Ethernet/description.odt text description] – [http://ohm.bu.edu/~hazen/CMS/SLHC/IPBUS_VHDL_description.pdf PDF]
     18
     19== Speed Tests 8/4/2010 ==
     20The latest version of the code (running at 1 Gbps connection speed) was tested to assess its proficiency at transmitting data.
     2150000 UDP requests and responses were generated in under 7 seconds. Each UDP response carried 1476 bytes of relevant data.
     22Therefore, the project is currently capable of 84Mbps data transfer rates or around 8% efficiency. It is not surprising that this
     23figure is so low--it takes the project at least as long to format its responses as it does to send them. Other such delays, on
     24both ends of the Ethernet cable and in both software and firmware, probably contribute similar latencies. For instance, running
     25Wireshark while this transfer occurs causes the process to happen about 30% slower. The same test took 11 seconds to complete
     26when it was run using a 100Mbs connection. This statistic implies a 54 Mbps transfer rate--mildly slower than at a 1Gbps connection
     27but significantly more efficient (54% rather than 8%). Almost all of the inefficiency at 100Mbps can therefore be attributed to
     28the board''s firmware and not deficiencies of the attached computer.
     29
     30== WIZnet TCP/IP Chips ==
     31
     32* [http://www.circuitcellar.com/archives/viewable/Eady208/index.html Circuit Cellar Article]
     33"iEthernet Bootcamp" •
     34[http://www.circuitcellar.com/archives/viewable/Eady207/2711015Eady.pdf PDF Version]
     35* Uses [http://www.wiznet.co.kr/products_main.htm Wiznet]
     36[http://www.saelig.com/miva/merchant.mvc?Screen=PROD&Product_Code=ETH027&Category_Code=ETH here]
     37* [http://www.wiznet.co.kr/pro_iin_w5100E01_avr.htm W5100E Eval Board]
     38* [http://ohm.bu.edu/~pbohn/W5100E01-AVR_Demo_Board/ W5100E Eval Board Software & Documentation]
     39
     40= Papers =
     41
     42* Microchip [http://ohm.bu.edu/~hazen/DataSheets/Microchip/01120a.pdf App Note 1120]
     43* [http://www.mhl.tuc.gr/research/publications/2005/DOLLAS_TCP_POSTER_83.pdf
     44  "An Open TCP/IP Core for Reconfigurable Logic"] – Technical University
     45 of Crete.  Very interesting... where is the core?
     46* [http://ieeexplore.ieee.org/iel5/10643/33584/01596997.pdf?arnumber=1596997
     47 "An analysis of FPGA-based UDP/IP stack
     48parallelism for embedded Ethernet connectivity"] –
     49  Mälardalen University, Västerås, Sweden
     50* [http://www.diva-portal.org/diva/getDocument?urn_nbn_se_liu_diva-2398-1__fulltext.pdf
     51  "EVALUATION OF PICOBLAZE AND IMPLEMENTATION OF A NETWORK INTERFACE"]
     52  – interesting but incomplete description of a Picoblaze MAC
     53
     54=== Embedded Software TCP/IP ===
     55* [http://www.sics.se/~adam/uip/index.php/Main_Page uIP]
     56* [http://ohm.bu.edu/cgi-bin/superk/Ethernet_Development SuperK Project Page]
     57  with information on micro-controller core based TCP/IP stacks
     58