wiki:Xilinx_Ethernet

This page contains design notes on logic implementation of TCP/IP protocols.

TCP/IP in Logic

Jeremy Mans "IPBUS"

'TriDAS/hcal/hcalUpgrade/src/common/RequestResponse.cc and 'TriDAS/hcal/hcalUpgrade/include/hcal/upgrade/IPbusCore.hh for Jeremy's library in C++.

VHDL version of IPBUS for Spartan 6 chips

Speed Tests 8/4/2010

The latest version of the code (running at 1 Gbps connection speed) was tested to assess its proficiency at transmitting data. 50000 UDP requests and responses were generated in under 7 seconds. Each UDP response carried 1476 bytes of relevant data. Therefore, the project is currently capable of 84Mbps data transfer rates or around 8% efficiency. It is not surprising that this figure is so low--it takes the project at least as long to format its responses as it does to send them. Other such delays, on both ends of the Ethernet cable and in both software and firmware, probably contribute similar latencies. For instance, running Wireshark while this transfer occurs causes the process to happen about 30% slower. The same test took 11 seconds to complete when it was run using a 100Mbs connection. This statistic implies a 54 Mbps transfer rate--mildly slower than at a 1Gbps connection but significantly more efficient (54% rather than 8%). Almost all of the inefficiency at 100Mbps can therefore be attributed to the boards firmware and not deficiencies of the attached computer.

WIZnet TCP/IP Chips

"iEthernet Bootcamp" •  PDF Version

 here

Papers

parallelism for embedded Ethernet connectivity"] –

Mälardalen University, Västerås, Sweden

Embedded Software TCP/IP