Changes between Version 5 and Version 6 of VHDLCoding

Timestamp:

Apr 20, 2020, 10:46:20 AM (4 years ago)

Author:

Eric Hazen

Comment:

--

VHDLCoding

@@ -20 +20 @@
 === Testbench Notes ===
 
-Problem:  how to handle a repeating clock and other synchronous signals, mixed with reading test vectors and asserting them.  
+Problem:  how to handle a repeating clock and other synchronous signals, mixed with reading test vectors and asserting them.  First, some suggestions on how to handle clocks.  Even calculating the period is a pain in VHDL due to the weird behavior of the 'time' type.  Clock and reset can be done without a process, so:
 
 {{{
@@ -27 +27 @@
   constant clk_per     : time     := (real(1e9)/real(freq)) * 1 ns;
   constant half_period : time     := clk_per/2;
+
+  signal clk : std_logic := '0';  -- init needed if clock done as below
 begin
   clk <= not clk after half_period;
@@ -32 +34 @@
 }}}
 
+Next question:  test vectors from file.  One approach is to have a scheduled launch time in the vector file, in clock ticks or BcN/OrN or some other scheme.  How to handle this?
+
 Internet references: