Changes between Version 5 and Version 6 of VHDLCoding


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Timestamp:
Apr 20, 2020, 10:46:20 AM (3 years ago)
Author:
Eric Hazen
Comment:

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  • VHDLCoding

    v5 v6  
    2020=== Testbench Notes ===
    2121
    22 Problem:  how to handle a repeating clock and other synchronous signals, mixed with reading test vectors and asserting them. 
     22Problem:  how to handle a repeating clock and other synchronous signals, mixed with reading test vectors and asserting them.  First, some suggestions on how to handle clocks.  Even calculating the period is a pain in VHDL due to the weird behavior of the 'time' type.  Clock and reset can be done without a process, so:
    2323
    2424{{{
     
    2727  constant clk_per     : time     := (real(1e9)/real(freq)) * 1 ns;
    2828  constant half_period : time     := clk_per/2;
     29
     30  signal clk : std_logic := '0';  -- init needed if clock done as below
    2931begin
    3032  clk <= not clk after half_period;
     
    3234}}}
    3335
     36Next question:  test vectors from file.  One approach is to have a scheduled launch time in the vector file, in clock ticks or BcN/OrN or some other scheme.  How to handle this?
     37
    3438Internet references:
    3539