Proposed USB readout for thermal neutron detector. A readout box with 4 inputs (BNC or LEMO) digitizes at 1MSPS signals from 4 summing amplifiers. Data is buffered in a RAM, and read out over USB (2.0 Hi-Speed mode) to a computer.

USB Readout 4 Channel Digitizer

• Schematic – ​SCH ​PDF
• Layout – ​PCB
• BOM – ​CSV • ​PDF
• Firmware – ​Project ZIP • ​VHDL ZIP
• Software – ​ZIP

PCB Notes

• The 0.1" pins for the JTAG connector did not fit into the PCB holes. The holes in the PCB file have been increased from 0.029" to 0.035". Test pins with a caliper before committing to this design in case the larger holes are still not big enough. The other problem with the board is that the SMA connectors are too close together. If SMA cables are used there is no problem. However, if BNC adapters are used, they are too big to use right next to each other. The solution is to order SMA to BNC cables, or move the SMA layout to accommodate the BNC adapters.

VHDL Notes

• Project was tested using Win7 32-bit using Xilinx ISE 13.2

'Memory Considerations

One "pulse" could be 1mS of recording, or 1k samples (2 bytes/sample). If we want to buffer i.e. 8 pulses per channel for 4 channels, this requires 64k bytes RAM. For full-speed operation, we need to be able to store 4 channels simultaneously (8k bytes/sec) plus readout perhaps 30k bytes/sec (depends on USB speed). A 25ns cycle time is adequate. <em>Must operate on 3.3V supply</em> to be compatible with CPLD.

Many possible choices include the Cypress CY7C1010DV33 (256Kx8) or CY7C1049DV33 (512Kx8).

• ​ADS7886
• FTDI ​FT232H
• ​IS61C5128AS-25TLI
• CoolRunner? II CPLD (XC2Cxxx) from Xilinx
• ​bus-blaster
• ​FT232H C code

'Drawings

• ​Block Diagram

'Initial Test Firmware

Please refer to:

• ​UM232H datasheet
• ​FT232H datasheet
• ​CoolRunner-II Evaluation Board
• ​XC2C256 CPLD

Read data could come from a counter or the slide switches, while write data can go to the LEDs.