Reference

• Tracker DAQ Development ​espace
• Data format: ​GitHub
• uDTC ​firmware (aka d19c) ​IT-firmware ​middleware
• uDTC ​manual (aka d19c)
• RD53A Chip: ​manual
  • RD53B Chip: ​Draft manual ​local copy 2020-05-29
• Aurora protocol ​specification (Xilinx) * ​10 GbE page 262+
• IT Services: ​shared documents ​Rates from 7/18
• Tracker TDR: ​TWiki (​local)
• LUMI talks: ​July 2018 ​Oct 2017
• ​DTH page ​TDCS2 page
• CMS DAQ: CmsPhase2Daq collection of links to Git repos, etc
  • ​Custom Hardware Network Interface Specification... for IP addresses etc
  • ​DTH spec ​Interface spec (updated April 2019) (​source)
  • Interim TDR: ​pdf ​DocDB
  • 2020-04-01 ​Talk with details of DTH and firmware
• LPGBT: ​ACES 2016 talk ​forums ​ACES 2018 talk ​Tutorial
• GBT-FPGA ​Project page
• Module Schematics, start at ​https://espace.cern.ch/Tracker-Upgrade
  • Click "Pixel Module, then "Libraries->Documents->CROC HDI Schematics"
• LpGBT ​Manual ​LpGBT-FPGA
• VL+ ​site ​TWEPP19 ​EDMS (Samtec specs)
• Compression/Readout: ​Yangyang talk Nov 2017
• YY Pixel Layout: ​drawings
• ​status Dec 2016
• Data Compression: ​Androsov July 2016
• DTC Rates: ​Spreadsheet from Mark P/Stella O 6/14/18
  • DTCChipsLinksTable -- table from Andreas with links/DTC and chips/DTC
• Serenity: ​talk Oct 2017
• uDTC: ​eSpace
• ​Trk BE gitlab
• ​TIF Twiki

• TrackerDTCFirmwareNotes -- notes on firmware
• UsefulSlideReviewOct2019

Cost/Schedule

• ​Peter's Budget (Dropbox link)
• ​BU Proposal (SVN link to current PDF)

Documentation

• SVN: ​http://gauss.bu.edu/svn/cms-tracker (see ​Meetings folder for BU-created slides)
  • ​DTCProposal_BU -- draft proposal / SOW by Zeynep
• PixelDTCDesignNotes
• AuroraProtocolDevelopment -- starting work on Aurora encode/decode
• Simulation Studies for IT DTC
• PixelGeometryExplained for the befuddled

Obsolete outer tracker stuff

• ​Eva Oct 12th DTC update
• ​Outer Tracker (Indico)
• ​CMSTrackerWeek12May2016_DTC.pdf -- Useful DTC talk by F. Vasey from May 2016 tracker week

Notes

• 72 inputs (9.6 Gb/s) and 30 outputs (25 Gb/s)
• 100G to DAQ (?) so 4 additional 25G. Should plan for 8 for two DAQ cards so total 72 GTH, 38 GTY
• FPGA options for one device:

Part	Package	GTH	GTY
XCVU190	A2577	60	60
XCV7190	A2577	60	60
XCVU9P	A2577		120
XCVU13P	A2577		128