wiki:TRM_Interface

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Two computer interfaces are envisioned.

USB Interface

The Phase I interface will be based on a USB emulated serial port. A USB-to-serial converter chip is provided on the Nexys 3 development board, which converts the USB protocol into the standard asynchronous serial protocol described here

A device called a UART convert asynchronous serial data into a stream of bytes which can be interpreted by logic in the FPGA. The UART functions are available in the following archives from Xilinx (edf username and password).

Ethernet Interface

Last modified 9 years ago Last modified on Nov 8, 2013, 10:17:53 AM