This serves as a log of attempts to debug the 4 Channel ADC prototype board.

2017-08-04

Figured out bit scrambling given current register settings by "--start" option in adc program. Using script ​test_bits.sh:

root@pz_7030_2015_4:/rootfs# sh test_bits.sh
Writing 0x1
Bytemode is currently set to: 0x1
0001  0x000  0x010  0x010  0x010
0001  0x800  0x020  0x020  0x020
0001  0x000  0x004  0x004  0x004
0001  0x200  0x008  0x008  0x008
0001  0x000  0x001  0x001  0x001
0001  0x080  0x002  0x002  0x002
0001  0x000  0x400  0x400  0x400
0001  0x020  0x800  0x800  0x800
0001  0x000  0x100  0x100  0x100
0001  0x008  0x200  0x200  0x200
0001  0x000  0x040  0x040  0x040
0001  0x002  0x080  0x080  0x080

Implement descrambling in python script ​unscramble.py

How to collect data and make a plot:

  .../rootfs# ./adc --start   (required once to sync)
  .../rootfs# ./adc -F > output.txt
    (copy output.txt to another machine, or mount /rootfs remotely)
  $ ./unscramble.py output.txt > output.dat
  $ gnuplot
  > plot "output.dat" using 0:3 with lines   (3 is the channel number+1)

Observe that full scale on ADC is about 3.4V pk-pk on SMA input.

There is a discontinuity at values where (adc mod 64) is near zero. Here is a sample plot, at 200kHz, 1V peak-peak:

As of now the default ADC register settings are:

   0x00, 0x000	default (all powered, internal ref)
   0x04, 0x000  default (gain 1)
   0x0A, 0x000  default (2's compliment, ADC operation)
   0x0B, 0x061  custom pattern (n/a)
   0x0C, 0x001  custom pattern (n/a) 0dB gain
   0x0D, 0x481  override, bit-wise, 2-wire
   0x10, 0x143  100 ohm clk, 2.5mA, double LVDS curr
   0x11, 0x005  data term 166 || 250 (why?), 1X frame clock

So, let's try byte-wise mode. Change 0x0d from 0x481 to 0x401. Take some data. Now there's another problem, likely with bit 9 (mod 512).

Potentially Useful Observations:

• Sometimes the system loses bit sync and is off by e.g. 4 bits. This seems to happen when changing the pulse generator settings. Could be due to the fact that the 100MHz sampling clock for the ADC is generated by the signal generator and might glich when changing settings.
• Bit-wise and byte-wise mode have (different) data-dependent problems. My theory is that the deserializer is causing this. Time to dive into Joshua's VHDL.

Clock Replacement

Date

20 Jul

Attempted fix

Replace erroneous CMOS clock used on board with LVDS alternative.

Method

Remove on-board clock, connect waveform generator to pads and simulate 100MHz LVDS signal.

Result

Upon power up, the outbound differential pairs began transmitting.

Current Draw

Date

20 Jul

Attempted fix

Use digital multimeter to measure current draw when the configuration RESET pin is brought high then low.

Method

One multimeter was used in series with the power supply to measure current draw, while a second one was used to confirm the voltage on the RESET pin was changed.

Result

Upon reset, there was no change in current when RESET was toggled.

Parallel Configuration Pins

Date

19 Jul

Attempted fix

Use parallel config instead of serial config, in case the issue lies with the serial configuration method.

Method

RESET is tied HIGH, CFG1 and CFG2 are tied HIGH, SCLK and SDATA are tied LOW, and SEN is tied HIGH. The board was supplied 12V from an adjustable power supply.

Result

Upon power up, the outbound differential pairs reported 0V relative to ground.

Config Pin Startup Behavior Adjustment

Date

18 Jul

Attempted fix

Change SCLK and SDATA so they default to HIGH when not in use, as reflected on the ADC datasheet.

Method

The change was implemented and firmware was re-synthesized.

Result

Upon power up, SCLK and SDATA were HIGH when not in use, but the outbound differential pairs reported 0V relative to ground.

SCLK Timing Adjustment

Date

17 Jul

Attempted fix

Change the behavior of SCLK to become active only when writing register data to the ADC, instead of SCLK being active all the time.

Method

The change was implemented and firmware was re-synthesized.

Result

Upon power up, SCLK was only active when writing register data, but the outbound differential pairs reported 0V relative to ground.

Inductor Replacement

Date

14 Jul

Attempted fix

Replace the inductor on the bottom of the board with a 1A fuse.

Method

The inductor was removed and a 1A fuse was substituted in its place.

Result

Upon power up, the fuse remained intact, but the outbound differential pairs reported 0V relative to ground.

Config Pin Breakout

Date

11 Jul

Attempted fix

Move SCLK, SDATA, SEN, and RESET off the FMC Connector and to a PMOD (JZ1-4) so that config signals can be transmitted at 3.3V instead of 1.8V.

Method

The change was implemented and firmware was re-synthesized.

Result

Upon power up, register data could be read from the PMOD Connector, but the outbound differential pairs reported 0V relative to ground.