Changes between Version 6 and Version 7 of QuadPulserRev1DebugLog


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Timestamp:
Aug 4, 2017, 11:35:27 AM (5 years ago)
Author:
Eric Hazen
Comment:

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  • QuadPulserRev1DebugLog

    v6 v7  
    6565
    6666* Sometimes the system loses bit sync and is off by e.g. 4 bits.  This seems to happen when changing the pulse generator settings.  Could be due to the fact that the 100MHz sampling clock for the ADC is generated by the signal generator and might glich when changing settings.
     67* Bit-wise and byte-wise mode have (different) data-dependent problems.  My theory is that the deserializer is causing this.  Time to dive into Joshua's VHDL.
    6768
    6869