| | 24 | |
| | 25 | === Test on existing HW === |
| | 26 | |
| | 27 | * Switch picoblaze comms back to USB/serial |
| | 28 | * Add registers to explicitly set ISERDES delays on both ends (Zynq, picoblaze) |
| | 29 | * Test / verify high speed serial comms (all 4 sets of FMC connections) |
| | 30 | * Restore simple ADC capture/readout via picoblaze |
| | 31 | * Test all ADC inputs and protection board |
| | 32 | * Test all SMA I/O and DB-9 as much as we can |
| | 33 | |
| | 34 | === New hardware rev === |
| | 35 | |
| | 36 | * ADC board |
| | 37 | * Check/correct all relevant ECOs |
| | 38 | * Check sequencer output resistors |
| | 39 | * Fix oscillator pinout |
| | 40 | * Check flash memory part number / footprint |
| | 41 | * Add pin 1 mark on U5 (check all footprints for orientation marking) |
| | 42 | * Move vias out from under chips (review layout for test probing and mods) |
| | 43 | * Change level shifter package |
| | 44 | * Delete all switching converters |
| | 45 | * Add power connector for all bulk voltages |
| | 46 | * Mounting holes for power board too |
| | 47 | * Check ADC channel number order |
| | 48 | * Ensure test points on every PS voltage, label test points on silkscreen |
| | 49 | * Convert front-end amps to 5V only (vs -1, +4) |
| | 50 | * Add two 5V LDO regulators for level shifters and ADC |
| | 51 | * Fix DB-9 buffer problems |
| | 52 | * Convert bi-directional SMAs to use two FPGA pins (in, out) |
| | 53 | * Larger series resistors on LEDs |
| | 54 | * FTDI serial vs HDMI serial (jumpers / duplicate I/o?) |
| | 55 | * New interface connector Micro-HDMI |
| | 56 | * Power supplies |
| | 57 | * Consider design of mezzanine board, or a single master power supply board |
