Changes between Version 4 and Version 5 of PixelDTCDesignNotes


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Timestamp:
Oct 3, 2018, 10:41:59 AM (4 years ago)
Author:
Eric Hazen
Comment:

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  • PixelDTCDesignNotes

    v4 v5  
    44 * See esp page 23 on for scrambler/gearbox details
    55* 8b10b vs 6466 coding: [http://ohm.bu.edu/~hazen/CMS/InnerTracker/8B10B_Coding.pdf 8B10B_Coding.pdf]
     6
     7== On-board RAM ==
     8
     9DAQ output estimate for one DTC is about 400 Gbit/s
     10
     11Maximum (component) DDR4 speed is 2400 Mb/s
     12
     13So, R/W of all data would require 333 bits and is therefore completely excluded.  We will not be buffering
     14the data in RAM. 
    615
    716== DAQ Outputs ==