Finding Stuff

• ​http://zedboard.org/support/design
  • Download BSP for Vivado 2018.2 here

2019-03-28

Even 2018.2 doesn't really work under Ubuntu 2018.4. Heading off to VM-land. Already have a 2016.4 VM.

2019-03-20

Looking into UIO drivers for Linux. See these threads:

• ​https://www.osadl.org/fileadmin/dam/rtlws/12/Koch.pdf -- Very useful intro to UIO drivers
• ​http://fpga.org/2013/05/28/how-to-design-and-access-a-memory-mapped-device-part-one/
• ​https://forum.digilentinc.com/topic/16550-uio-access-including-interrupts-when-using-petalinux/#comment-40229
• ​https://forums.xilinx.com/t5/Embedded-Linux/Petalinux-2017-2-no-UIO-devices-found/td-p/802250
• ​http://painlessdev.blogspot.com/2017/12/petalinux-from-scratch-using-xilinx_19.html
• ​http://microzedchronicles.com/

Hopefully this is documented better somewhere... looking

Looking to start now with Petalinux again. 2018.3 tools installed at /usr1 but don't work with multiple monitors (go figure!). Installing petalinux 2018.2 at /usr1/petalinux.

2019-03-19

• Following ​UG1165 to create a minimal design

In Vivado:

• Create a design based on the FMC Carrier with Picozed 7020
• Connected "FCLK_CLK0" to "M_AXI_GP0_ACLK".
• Ran synthesis, implementation, build bitstream

In SDK:

• Create a "hello world" project per UG1165.
• In "platform_config.h" change UART_DEVICE_ID to 1 and build (this may not be needed)
• Add xilffs library to BSP:
  • Double click system.mss and "Modify this BSP's Settings"
  • Find and enable xilffs library
• Create a new Application Project "eric_fsbl" referencing the existing BSP
• In "hello_world" project right click "Create boot image". Should be 3 partitions in boot image:
  • eric_fsbl.elf (from FSBL project)
  • design_1_wrapper.bit (from hardware design, bitfile)
  • hello_world.elf
  • This creates a BOOT.bin file
• See MakingBootableCard and copy to FAT partition

Managed to make a blinking LED on GPIO!

In Vivado:

• added an AXI GPIO
• set output width to 2
• figured out that the pins are named "gpio_rtl_tri_o[1:0]"
• added a constraint file:

set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS25 } [get_ports {gpio_rtl_tri_o[0]} ]
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS25 } [get_ports {gpio_rtl_tri_o[1]} ]

• Generated a new bitfile
• Did File->Export->Export Hardware
  • (SDK automatically picked up the change)

In SDK:

Added this stuff to the program (excerpt key parts only):

#define LED 0x01   /* Assumes bit 0 of GPIO is connected to an LED  */
#define GPIO_EXAMPLE_DEVICE_ID  XPAR_GPIO_0_DEVICE_ID
#define LED_DELAY     10000000
#define LED_CHANNEL 1
XGpio Gpio; /* The Instance of the GPIO Driver */
  ...
main() {
  int Status;
  volatile int Delay;
  XGpio_Initialize(&Gpio, GPIO_EXAMPLE_DEVICE_ID);
  XGpio_SetDataDirection(&Gpio, LED_CHANNEL, ~LED);

  while (1) {
    XGpio_DiscreteWrite(&Gpio, LED_CHANNEL, LED);
    for (Delay = 0; Delay < LED_DELAY; Delay++);
    XGpio_DiscreteClear(&Gpio, LED_CHANNEL, LED);
    for (Delay = 0; Delay < LED_DELAY; Delay++);
  }
}

Re-build all, make new boot image. It works!

Next step, user IP in VHDL.

Trying to follow this rather out-of-date tutorial:

​http://www.fpgadeveloper.com/2014/08/creating-a-custom-ip-block-in-vivado.html

It seems to work. Haven't actually tried running the code