2011-01-09

This plot is a threshold sweep of the noise rate for all channels of the first rev2 ASDQ setup.

Chip setup is the same as 2011-01-08, but doesn't have the 5mv offset added in.

2011-01-08

This plot is a comparison between an o-scope readout of the ASDQ and the TDC readout.

This setup uses the second revision of the ASDQ board and has no sockets installed so the input to the ASDQ has a capacitor to a 10ohm resistor to the input of the ASDQ.

There was a small (5mv) difference between what the TDC DAC is set to and the actual value measured by the o-scope so a 5mv shift was added to align the plots.

TDC + ASDQ board current draws

Setup	+V current	-V current	+V	-V
TDC only	42mA	NC	?	?
TDC + ASDQ	96mA	NC	?	?
TDC + ASDQ	319mA	242mA	3.75	-3.8
TDC + ASDQ with firmware and no clock	650mA	300mA	3.75	-3.8
TDC + ASDQ with firmware and clock	480mA	275mA	3.75	-3.8

Raw ASDQ noise rate

This plot is generated by monitoring the input voltage and the ch 0 LVDS output of the ASDQ board #2.

The frequency is the count of cycles in a 20us window.

NOTE: PLOT BELOW IS NOT REPRODUCIBLE AT THIS TIME'''

ASDQ board 2

This plot is the output of ASDQ chip 1, channel 0 as a function of DThresh.

This channel on the board is not connected to any external components.

This plot is the output of the ASDQ chip 2, channel 7 as a function of DThresh.

This channel on the board is connected by a ~1" wire to 1pC to 50 Ohms to ground.