This gizmo accepts a 10 or 20MHz reference clock and provides two sets of (4) ECL-level differential programmable outputs. The output frequency is set according to the table below.

JP1/JP3	JP2/JP4	Mult	Out/10MHz	Out/20MHz
L	L	4X	40MHz	80MHz
L	-	5.3125X	53.125MHz	N/A
L	H	5X	50MHz	N/A
-	L	6.25X	62.5MHz	N/A
-	-	2X	20MHz	40MHz
-	J	3.125X	31.25MHz	62.5MHz
H	L	6X	60MHz	N/A
H	-	3X	30MHz	60MHz
H	H	8X	80MHz	N/A

Notes:

The jumper set JP1/JP2 controls the outputs J1-J4. The jumper set JP3/JP4 controls the outputs J5-J8.

"L" or "H" means install a jumper between the middle pin and the upper or lower pin. "-" means do not install any jumper (or "park" the jumper so it doesn't connect any pins).

Both sets of outputs are fed by the common BNC input, which requires a 1-3V peak-to-peak square or sine wave input with approximately 50% duty cycle.

PCB Documentation

The PCB layout was done with ​ExpressPCB

• Schematic: ​SCH ​PDF
• PCB Layout: ​PCB ​PDF

Here is the specification we were given:

We have the following CAEn units that need either 40 or 50 MHz:

WFD (all need 50 MHz driver frequency, I think ECL of some form)
DT5730, 500 MHz, desk top   3-102203-4 connector, LVDS/ECL/PECL/LVPECL (100 ohms ac-coupled)
DT5720, 250 MHz, desk top   (same)
V1724, 16 MHz, VME          (same)
V1720, VME, not sure of frequency  (same)

TDC (needs 50 MHz driver frequency, I think ECL of some form)
V1290N  two 3M 3408-5202  Not clear if Ac- or Dc- coupled