David Somers (somers@…) in Psychological & Brain Sciences

Evolving Design

Shopping List

  • ESB30K-ND (heat shrink cap)
  • 3600B/24 100SF cable (12 pairs, braid+foil shield)


  • Sean Tobine (sp? 4th year GS)
  • Christopher Moore (with Brown U collaborator)
  • Michael Beauchamp (Texas)
 Tactical stimulator (5 fingers, piezo) for use in MRI (3T field)
 BNC cables to feed-thru (2 BNC per piezo) or alternatively DB-25
 MATLAB libraries on Mac for control ("psych toolbox" library)
 Freq, time stimulus, order ms or 10's ms resolution
 Essentially they want a menu of 4-5 different freqs for use
 within an experimental run.


DRV2700 Design Notes

Output is 105V max without a booster, while the piezos we're considering are 200V max.

Development Log

2018-12-12 Final testing The device finalized on 12/12 takes around 3.5A to run all five channels at maximum amplitude.

2018-11-28 Further Testing Several tests were conducted with the new adapter (proper pinout). The power supply had been set to a limit of 1A, and was raised to 4A, which solved the Over-Current Trip. Some notable happenings: Testing the New device (has not been to the Somers Lab) versus the Old (Has sat in the Somers Lab) device revealed that the Old device draws about 0.1A more than does the new device. The Old Device with the Old (Blue-box/earlier shipment) piezos produced a louder and cleaner sound than did the New device. With the lower power supply current limit, both devices trip at relatively low levels (0x80 - 0xc0 on the hex output scale) With the higher power supply current limit, neither device trips.

2018-11-28 Findings

The 4-pin to 3-pin adapter used previously in testing has a different pinout than the Piezo Inductor Board used in the setup:

  • The Piezo Inductor Board uses the pinout: SIG,GND,BST
  • The 4-pin to 3-pin adapter used the pinout: GND,SIG,BST ( GND and SIG are switched )
  • Three old-batch piezos, previously installed in a fully working setup (tested in MRI), are wired with pinout: SIG,GND,BST
    • These piezos have been labeled today as A, B, and C.
  • Two new-batch piezos, labeled today as D and E, are wired with pinout: GND,SIG,BST
  • One new-batch piezo, labeled today as F, is wired correctly for the 4-pin driver board outputs: GND,SIG,NC,BST

Therefore, it is suspected that GND and SIG were wired incorrectly during previous testing.

A new 4-pin to 3-pin adapter has been made with the pinout: SIG,GND,BST (in agreement with Piezo Inductor Board Rev.A) New-batch piezos D and E will be rewired to this pinout, and tests will be repeated for all six piezos.

2018-09-26 Test

Conducted another test with the piezo wires closely braided. No problems this time. For Sean's use, the current setup is thought to be usable.

To-Do list for future systems:

  • Cable clamps to strain relief piezo wires on lid/box near header
  • Clamp or otherwise attach piezo wires to finger/thumb holders
  • Design and fabricate a housing for the in-line inductor board
  • Add a small fan to the Raspberry Pi box
  • Change long cable connector to non-magnetic one (connector housing??)
  • Design better cover for inductor board on piezo stimulator

2018-09-05 Test

Tested the setup in the MRI for the first time. Thumb piezo arced. Wires to piezo were not twisted or otherwise dressed. It is likely the thumb wire had a significant loop which picked up RF, causing the arc.

2018-06-19 Meeting


  • The SIF will make an initial mechanical prototype of the piezo holder, with the following mods:
    • Extend the back portion by about 3 inches beyond the most rearward position of the movable piezo holders
    • Add an array of holes on 1/2 in centers for cable ties, etc
  • The EDF (Hugo) will wire a cable with (4) piezos on one end and connectors suitable for the electronics on the other end.
  • David Somers will put his undergrad working on software in direct contact with Hugo


We figured out some more scripting today - changing parameters of one, multiple, or all drivers and buzzing separately is possible.

Setting both two 440Hz and buzzing immediately:

Setting both two 880Hz and buzzing immediately:

Setting up all channels separately then buzzing:

after setup, changing frequency and duration of each channel individually:

Additionally, the piezo drivers have been shown to be capable of operating at the same time:

The four write blocks are writing to four different channels - the maximum amount of writing to be done on the board after setup. Two channels are hooked up to the scope - one receiving 120Hz as its frequency directive and the other 60Hz. Each write could be off by up to 2%, as the driver chip


We wrote code that pre-programs the RAM and calls on it to play prewritten waveforms There is roughly a 1ms delay between selecting a waveform and playing it on the piezo, as shown below.

Thus we can expect a 2ms delay before buzzing should we also write to select a mux before selecting and writing to the piezo driver.


Below is a block of the code from Chris Black at Brown with comments added to explain how the code writes to the RAM and how to write waveforms.

    # Control
    drv.write_byte_data(DRV_ADDRESS, 0x02, 0x00) # Write STANDBY to off, meaning writes are enabled HL
    drv.write_byte_data(DRV_ADDRESS, 0x01, _DIGITAL_GAIN_[gain]) # Writes gain value of 50 V; should write bits 6:3 as all high for CHIPID HL
    drv.write_byte_data(DRV_ADDRESS, 0x03, 0x01) # Upon seeing of the GO bit, play waveform ID 0x01 HL
    drv.write_byte_data(DRV_ADDRESS, 0x04, 0x00) # Writes null to 0x04 s.t. after 0x01 piezo stops  HL

    # Header
    drv.write_byte_data(DRV_ADDRESS, 0xFF, 0x01) # Opens RAM for writing                            HL
    drv.write_byte_data(DRV_ADDRESS, 0x00, 0x05) # Declares header to be size 5*5+1=26              HL
    drv.write_byte_data(DRV_ADDRESS, 0x01, 0x80) # Start address upper byte, basically mode + page
    drv.write_byte_data(DRV_ADDRESS, 0x02, 0x06) # Start address lower byte, start position on page
    drv.write_byte_data(DRV_ADDRESS, 0x03, 0x00) # Stop address upper byte, page number
    drv.write_byte_data(DRV_ADDRESS, 0x04, 0x09) # Stop address lower byte, end position on page
    drv.write_byte_data(DRV_ADDRESS, 0x05, 0x01) # Repeat number for waveform

    # Data
    drv.write_byte_data(DRV_ADDRESS, 0x06, amp)  # RAM waveforms stored in order Amplitude          HL
    drv.write_byte_data(DRV_ADDRESS, 0x07, freq) #                               Frequency          HL
    drv.write_byte_data(DRV_ADDRESS, 0x08, dur)  #                               Duration           HL
    drv.write_byte_data(DRV_ADDRESS, 0x09, env)  #                               Envelope           HL

    # Control
    drv.write_byte_data(DRV_ADDRESS, 0xFF, 0x00) # Exits RAM writing mode and sets to control mode  HL
    drv.write_byte_data(DRV_ADDRESS, 0x02, 0x01) # Writes 0x01 to ctrl; boost off and writes GO hi  HL


The first image is the buzz signal (measured on a scope and not attached to a piezo) as it appears the first time after the function is called. For some reason the runtime is longer than the individual time (end of last i2c transaction to first buzz) by anything from 1-10ms.

These timing diagrams affirm that the delay due to i2c transactions is on the order of 10ms for a normal-sized command.

The second buzz after the function call (and subsequent buzzes) take less time (on the order of 0.1ms=100us).

Below is an image of a non-initial buzz triggering on the Out signal as opposed to the I2C lines

The following two images show delays of 700us and 11ms between the first write and the first buzz, depending on whether or not the waveform gets rewritten before each buzz GO write.

2018-05-23 Some messy code is written and the piezo board is up and running. The time separation between the beginning of a GO write and the buzzing of the piezo is 0.54ms (536us), as displayed in the image below:


Meeting yesterday. Proposed plan:

  • DB-25 connector feed-thru the patch panel
  • Multi-conductor shielded cable with 3 wires min per piezo (better two twisted pairs per) so total 4x5 = 20 cond plus shield
  • Connector like 39-01-2200 or similar on the MRI end



  • J1 wrong pitch OK HL
  • 603 pad, 402 component: R28 R33 R38 R43 R48; R29 R34 R39 R44 R49; R30 R35 R40 R45 R50 OK HL
  • C3, C4 - Not on BOM
  • J4, J10, J11, J12, J13 - Not on BOM
  • J2 - part does not fit; slots became circular holes
  • U3 - Wrong Footprint width OK HL
  • Q1 - needs label pin 1 mark OK HL
  • U4-U8 - part is missing from kit OK HL
  • L1-L5 - part is missing from kit OK HL
  • C13, C20, C27, C34, C6 - part is missing from kit OK HL
  • J5 J6 J7 J8 J9 - wrong P/N called out, designated wrong pitch

HL To-do: Propagate changes from BOM to KiCad? file so the BOM will be accurate when generated in the future

2018-02-27 Looking at FyberLabs? board design

Updating BOM with in-stock parts

Ref Value Their P/N Stock P/N DigiKey?
C1 0.1uF 250V X7R C2012X7T2E104M125AA CGA4J3X7T2E104K125AE 445-8778-1-ND
C2 100uF CL31A107MQHNNNE C1206C107M9PACTU 399-5620-1-ND
C3 0.1uF 16V CL21B104MOCNBNC yes 1276-2452-1-ND
C4 1uF 10V CL14A105MP5NANC ECJ-UVB1A105M P11984CT-ND
L1 4.7uH 1.8A 20% LPS4018-472MR yes 994-LPS4018-472MRC (Mouser)
R1 768K ERJ-2RKF7683X yes P768KLCT-ND
R2 13k for 150Vmax ERJ-2RKF1302X P13.0KLCT-ND
R3 7.87k ERJ-2RKF7871X YES P7.87KLCT-ND
R4 4.7k EXB-24V472JX yes Y5472CT-ND
U1 DRV2667RGPT yes 296-38930-1-ND

2018-02-26 Alternative board design

Chris at Brown pointed out this board:

They are $40 assembled by "FyberLabs?" but out of stock now. Could get a batch made by Osh park?

2018-02-23 External analog input.

  • Remove JP5 and JP6 to disconnect MSP430 output
  • Set JP7, JP8, JP9 to pull-up to force enable and max gain
  • Apply input to AIN+ (AIN- can be open)

For external power:

  • Move JP10 to VIN
  • Supply 5V on J2 (screw terminals)

Something bad happened and now the 3.3V supply is gone and probably the uC. It does still work with external input to the DRV2700 though the gain seems low.

Reconnect to external power and signal gen. Seems OK.

Signal gen set to "2V". Measure 1.5V pk-pk on TP7 and 85V pk-pk on output. This is a gain of 56 which is around 35dB. Somewhat less than the advertised 40.

Now working on signal generator control. Looking at the manual. It says to use port 5024 for Telnet and 5025 for socket sessions.


  APPL:SIN 400 HZ, 1.5V, 0

2018-02-22 trying to wire up a Piezo. See pictures. Wire as follows:

  • Black to GND
  • Blue to OUT-
  • Red to BST

It works! Close JP2, JP3, JP4 to get ~100V power, now get up to 50V output.

2018-02-21 have a DRV2700EVM eval module. Trying to run the software in Vbox on thinkpad. Failed miserably, but it does work on the "big printer" windows machine.

Mechanical Setup

DB-25 pinout

Pin # Channel Sig. Type
1 1 Signal
2 1 Ground
3 1 Boost
4 1 Ground
5 2 Signal
6 2 Ground
7 2 Boost
8 2 Ground
9 3 Signal
10 3 Ground
11 3 Boost
12 3 Ground
13 4 Signal
14 4 Ground
15 4 Boost
16 4 Ground
17 5 Signal
18 5 Ground
19 5 Boost
20 5 Ground
Last modified 3 days ago Last modified on Dec 12, 2018, 11:48:54 AM

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