2017-10-03 (hazen)

According to Stephen in today's meeting, we do want to run the GBT-FPGA core and the associated MGT cores at half speed, so the GBT "frame clock" will be 20MHz. So in ngCCM.vhd the TX_Clock_40MHz and RX_Clock_40MHz inputs will now be 20MHz.

Also here the input and output are mapped to bits (asynchronously):

  -- Assign the output pins to TX_Word.
  TX_Word_o       <= ngCCM_Pins_to_GBT_Word(ngccmPinsOutReg);
  prbs_write_regs <= ngccmPinsOutReg.prbs_rx;
  -- Assign RX_Word_tx40 to the virtual input pins
  ngccmPinsInReg  <= GBT_Word_to_ngCCM_Pins(RX_Word_tx40);

ngccmPinsInReg is assigned various things (notably from data_in()) in a clocked process using TX_Clock_40MHz. This data_in() comes from an instance of IPbus_local, which has it's clk_local connected to TX_Clock_40MHz.

2017-09-29 (hazen)

Looking at Stephen's e-mail of 2017-09-29:

However, I did want to make sure you were up to date on the changes to the GBT bits to handle the half bit rate.

Basically, the “secondary” bits which occupied the odd numbered bits in the GBT Frame are now the falling edges for the primary (and only) bits. This allows a 40 MHz signal to be encoded in the 20 MHz GBT Frame. This is basically the way the GBTx ASIC handles 80 MHz signals from a 40 MHz Frame.

The way I handle this in the ngCCM is in the VHDL files Igloo2_Data_Up_Half.vhd and Igloo2_Data_Down_Half.vhd. They can be compared to Igloo2_Data_Up.vhd/Igloo2_Data_Up_Sync.vhd and Igloo2_Data_Down.vhd/Igloo2_Data_Down_GF.vhd which are used in Full bit rate mode.

The latest code can be found ​here (SVN link)

The GBT frame bit definition (which I just updated) can be found here: ​HEHB_ngCCM_Half_Speed_GBT_Bits_v4.xlsx

The bit mapping happens in a function GBT_Word_to_ngCCM_Pins in ​ngCCM_package.vhd plus the reverse function GBT_Word_to_ngCCM_Pins.

Superficially it seems as if one can just edit these functions per Stephen's spreadsheet.