June 2014 Prototype Review

Reference Information

Design Comments

  • Maybe more bypass caps on DDR3 VREFs. See AMC13XG T1 schematic: T1.PDF (page 4) for a known working design.
  • Is a resistor divider sufficiently low impedance for DDR3 VREFs? Might consider a switching regulator like the TPS51116RGER (page 7 of AMC13 schematic).
  • Recommend GND on debug headers
  • I notice that the MMC is not wired to the FPGA in the way we have done it (we have an SPI bus used for configuration R/W from the MMC to the FPGA). Therefore I'm assuming you have forked the MMC code and are taking care of all the pin assignments yourself.
Last modified 9 years ago Last modified on Jun 7, 2014, 5:29:57 PM