A proposal has been requested to produce a new version of the FLARE timing board which is simplified and inexpensive to produce.  The processing chain of the existing design is as follows:

* [http://ohm.bu.edu/~hazen/Frangioni/TimingBoard/SchematicImages/Gating_FPGA_V1.0_full.png Top-level schematic]
 * [http://ohm.bu.edu/~hazen/Frangioni/TimingBoard/SchematicImages/PreProcessing.png Preprocessing stage]
  * [http://ohm.bu.edu/~hazen/Frangioni/TimingBoard/SchematicImages/DiffInput.png instrumentation amp]
  * [http://ohm.bu.edu/~hazen/Frangioni/TimingBoard/SchematicImages/LowPass.png low pass]
  * [http://ohm.bu.edu/~hazen/Frangioni/TimingBoard/SchematicImages/HighPass.png high pass]
  * [http://ohm.bu.edu/~hazen/Frangioni/TimingBoard/SchematicImages/TunableGain.png tunable gain]
  * [http://ohm.bu.edu/~hazen/Frangioni/TimingBoard/SchematicImages/AbsValue.png absolute value]
 * [http://ohm.bu.edu/~hazen/Frangioni/TimingBoard/SchematicImages/PhaseLock.png phase lock]
  * [http://ohm.bu.edu/~hazen/Frangioni/TimingBoard/SchematicImages/Level_Pulses_full.png level and pulses]
  * [http://ohm.bu.edu/~hazen/Frangioni/TimingBoard/SchematicImages/DiffFilter_full.png diff filter]
  * (plus some miscellaneous logic).


== Documentation ==

* [http://ohm.bu.edu/~hazen/Frangioni/TimingBoard/ TimingBoard]