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version from Bill

  • using SDRAM by Mr Wu
  • Working example of a simple design using SiTCP. Unfortunately a bit of a mess, as it was adapted from the original SiTCP example design in verilog long ago.


of SiTCP files plus

E-mail from Wu

  • Parameters are set as follows:
    • UDP port number: 0x1234
    • TCP port number: 0x17
    • MAC address 02:00:c0:a8:00:20
    • I/P address
    • MSS 1460 (decimal)

Xilinx Spartan-3E Starter Kit board

Last modified 10 years ago Last modified on Nov 8, 2013, 10:17:53 AM