Non-project Mode

Here is the simplest possible (?) build script for a Vivado project:

# create_project -force proj1 ./proj1
# read_vhdl proj1/src/top.vhd
# read_xdc proj1/src/pins.xdc
synth_design -top top -part xc7a12t-cpg238-1
opt_design
place_design
route_design
write_bitstream -force proj1/proj1.bit

Here is a sample (working) constraints file with the minimum stuff in it:

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 2.5 [current_design]

set_property -dict { PACKAGE_PIN k17 IOSTANDARD LVCMOS25 } [get_ports clk]
set_property -dict { PACKAGE_PIN n19 IOSTANDARD LVCMOS25 } [get_ports rst]
set_property -dict { PACKAGE_PIN n17 IOSTANDARD LVCMOS25 } [get_ports a]
set_property -dict { PACKAGE_PIN p18 IOSTANDARD LVCMOS25 } [get_ports b]
set_property -dict { PACKAGE_PIN r19 IOSTANDARD LVCMOS25 } [get_ports y]

For completeness here is a minimal VHDL file which works with the above

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity top is
  
  port (
    clk  : in  std_logic;
    rst  : in  std_logic;
    a, b : in  std_logic;
    y    : out std_logic);

end entity top;

architecture arch of top is

begin  -- architecture arch

  process (clk, rst) is
  begin  -- process
    if rst = '0' then                   -- asynchronous reset (active low)
      y <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      y <= a and b;
    end if;
  end process;

end architecture arch;