Quick simulation from command line

Create init.tcl and pulser.vhd

  xvhdl pulser.vhd
  xelab -debug typical pulser -s pulser_sim
  xsim --gui pulser_sim -t init.tcl

Omit the --gui and end the tcl script with quit to run in batch mode. Here is a simple example, to test a 4x4 multiplier with inputs (a,b) and output p:

puts "Starting multiplier test"
set errz 0
for {set i 0} {$i < 16} {incr i} {
    for {set j 0} {$j < 16} {incr j} {
	add_force a -radix dec $i
	add_force b -radix dec $j
	run 10
	set calc_p [expr {$i * $j}]
	set sim_p [get_value -radix unsigned p]
	if {$calc_p != $sim_p} {
	    puts "ERROR: Calculated: $calc_p simulated: $sim_p"
	    incr errz
puts "$errz total errors"

Building in Non-project Mode

Below is the simplest possible (?) build script for a Vivado project. Here is a fancier one from this blog fancy_build.tcl.

# create_project -force proj1 ./proj1
# read_vhdl proj1/src/top.vhd
# read_xdc proj1/src/pins.xdc
synth_design -top top -part xc7a12t-cpg238-1
write_bitstream -force proj1/proj1.bit

Here is a sample (working) constraints file with the minimum stuff in it:

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 2.5 [current_design]

set_property -dict { PACKAGE_PIN k17 IOSTANDARD LVCMOS25 } [get_ports clk]
set_property -dict { PACKAGE_PIN n19 IOSTANDARD LVCMOS25 } [get_ports rst]
set_property -dict { PACKAGE_PIN n17 IOSTANDARD LVCMOS25 } [get_ports a]
set_property -dict { PACKAGE_PIN p18 IOSTANDARD LVCMOS25 } [get_ports b]
set_property -dict { PACKAGE_PIN r19 IOSTANDARD LVCMOS25 } [get_ports y]

For completeness here is a minimal VHDL file which works with the above

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity top is
  port (
    clk  : in  std_logic;
    rst  : in  std_logic;
    a, b : in  std_logic;
    y    : out std_logic);

end entity top;

architecture arch of top is

begin  -- architecture arch

  process (clk, rst) is
  begin  -- process
    if rst = '0' then                   -- asynchronous reset (active low)
      y <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      y <= a and b;
    end if;
  end process;

end architecture arch;

Building With IP in Non-Project Mode

Got this from an AR, not tested/confirmed:

create_project -in_memory -part xc7vx415tffg1158-2
read_ip ./local_pcs_pma/local_pcs_pma.xci
set_property target_language VHDL [current_project]
generate_target all [get_files ./local_pcs_pma/local_pcs_pma.xci]
Last modified 21 months ago Last modified on Mar 12, 2019, 12:59:57 PM