Changes between Initial Version and Version 1 of D0_DFE_IEEE-NSS_Paper


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Timestamp:
Nov 8, 2013, 10:17:54 AM (6 years ago)
Author:
hazen
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  • D0_DFE_IEEE-NSS_Paper

    v1 v1  
     1''''Conference Website''': http://www.nss-mic.org/2006/
     2
     3== Poster ==
     4
     5Two pages, to be printed and posted one above the other.
     6As presented at IEEE.
     7
     8* [http://joule.bu.edu/~hazen/my_d0/DFEA2_IEEE/poster_final.pdf poster_final.pdf]
     9
     10== Abstract and Summary ==
     11
     12''''Title''':  Hardware Aspects of the Upgraded D0 Central Track Trigger
     13
     14''''Abstract''':
     15
     16The D0 experiment at the Tevatron at Fermilab (Batavia, IL USA) was
     17recently upgraded to handle the expected increase in instantaneous Tevatron
     18luminosity for Run IIb.  As part of the upgrade, much
     19of the Level 1 Central Track Trigger system was replaced.
     20
     21A key element in the Central Track Trigger is the Digital Front-End
     22(DFE) system.  The DFE processes hits from the Central Fiber Tracker and
     23identifies track candidates by comparing fiber hits to predefined hit
     24patterns using combinatorial logic implemented in FPGAs. 
     25The original DFE worked well but suffered several limitations: It combined
     26pairs of fibers in the tracker on a single input to the track-finding
     27logic; it required a long elapsed time to download new firmware; and
     28the cable plant at the front of the DFE racks was difficult to manage.
     29
     30The new DFE system provides many improvements, while remaining
     31plug-compatible with the orignal.  It significantly improves
     32granularity in the track-finding logic, provides much faster firmware
     33update times, and eliminates completely the cable plant at the front
     34of the DFE racks.  A new controller module provides a gigabit ethernet
     35over optical fiber interface for control and initialization.  New
     36self-test features permit exercise of all DFE logic with
     37pre-programmed test patterns, allowing a complete test of each DFE
     38crate before installation.  A stand-alone tester was developed to
     39exercise all inputs and outputs of each DFE for design verification
     40and production testing.
     41
     42== Summary ==
     43
     44* [http://joule.bu.edu/~hazen/my_d0/DFEA2_IEEE/summary_17May06.pdf summary_17May06.pdf]
     45* [http://joule.bu.edu/~hazen/my_d0/DFEA2_IEEE/summary_14May06b.pdf summary_14May06b.pdf]
     46
     47=== Reference Material ===
     48
     49* http://www-d0online.fnal.gov/www/groups/cft/CTT/online/Overview/overview.html
     50
     51There is a previous IEEE submission linked from here and a poster:
     52
     53* http://www-d0online.fnal.gov/www/groups/cft/CTT/online/Overview/ctt_poster.pdf
     54* http://www-d0online.fnal.gov/www/groups/cft/CTT/online/Overview/ieee_ctt.pdf
     55
     56* http://www-d0online.fnal.gov/www/groups/cft/CTT/online/ctt_main.html
     57
     58* http://www-d0.fnal.gov/~mommsen/CTTperformance.pdf
     59