= Project APOLLO = || [[Image(http://ohm.bu.edu/~hazen/APOLLO/figs/apollo_200.png)]] || This is a project to develop a common ATCA blade which can be used for readout and triggering applications in LHC experiments. It is named after the Apollo program CSM spacecraft which separated into Command and Service modules. || [[Image(http://ohm.bu.edu/~hazen/APOLLO/gallery/cm.jpg, link=[http://ohm.bu.edu/~hazen/APOLLO/gallery/])]] [http://ohm.bu.edu/~hazen/APOLLO/gallery Photos] || == Quick Links == * Document SVN: http://gauss.bu.edu/svn/common-atca-blade * Hardware SVN: http://gauss.bu.edu/svn/common-atca-blade.hardware (BU Service Module) * !GitHub: https://github.com/apollo-lhc (Cornell Command Module) * DRAFT schematics: * Service module (carrier): [http://gauss.bu.edu/svn/common-atca-blade.hardware/Blade/trunk/pdf/carrier.pdf carrier.pdf] (Boston University) * Command module (mezzanine) local copy: [http://ohm.bu.edu/~hazen/APOLLO/atca_mezz_ku15p_vu7p_07Mar2019.pdf atca_mezz_ku15p_vu7p_07Mar2019.pdf] (Cornell University) * DRAFT specification (ATLAS specific for now): [http://gauss.bu.edu/svn/atlas-phase-2-muon-upgrade/Documents/Proto0_Blade/trunk/blade_with_schematic.pdf blade-with-schematic.pdf] == Aux boards == * [[ApolloClocksTestBreakout]] -- "PicoDTH" clocks breakout for ATCA J23 * [[DummyCommandModule]] -- Breakout/loopback for CM connectors == Rev A Comments == * {{{EN_ONE_JTAG_CHAIN}}} should have a pull-up/down and/or jumper so something sensible happens when the IPMC is not installed or programmed. * Serial comms between Zynq and CM should be possible without IPMC intervention. * How to turn on payload power with no IPMC installed/running? * JTAG (and other GPIO) signals must obey ENABLE/READY to avoid driving CM logic when not powered == Reference Material * [http://ohm.bu.edu/~hazen/edf_joule/PICMG/PICMG-3.0-R3.0_withErrata001.pdf ATCA spec] (password) * CMS ATCA use: [http://ohm.bu.edu/~hazen/CMS/TrackTrigger/IN2018_002.pdf IN2018_002.pdf] (update April 2019) * CMS DTH spec: [http://ohm.bu.edu/~hazen/CMS/TrackTrigger/IN2018_001.pdf IN2018_001.pdf] (update April 2019) * [https://gitlab.cern.ch/cms-tracker-phase2-backend-development-engineering CMS tracker repository] * [[Carrier specs]] * [[ZYNQ DBS]] - Zynq daughterboard information * [http://ohm.bu.edu/~hazen/DataSheets/ATCA/ENG_DS_3-1773445-8_0707.pdf TE Connectivity ATCA brochure] * Parts parts parts * TE 1766500-1 Zone 1 connector * TE 6469001-1 Zone 2 connector * TE 1-1469373-1-ND Guide module * Schroff 20818-160 front panel/handle kit * Elma 66-536-28 panel * 81-300-00 and 81-301-01 handles * 81-088-1 microswitch Consider making mezzanine board 7U high (277.8 mm, see [https://en.wikipedia.org/wiki/Eurocard_(printed_circuit_board) Eurocard info]). Depth probably non-standard ~ 200mm as standard depths 160mm and 220mm are not convenient. === P23 Connections (Base ethernet) || P23 Row || Port || Pair || Base Channel || Function || || 6 || 0 || tx || 2 || BI_DA (10/100 TX ) || || 6 || 0 || rx || 2 || BI_DB (10/100 RX ) || || 6 || 1 || tx || 2 || BI_DC || || 6 || 1 || rx || 2 || BI_DD || || 5 || 0 || tx || 1 || BI_DA (10/100 TX )|| || 5 || 0 || rx || 1 || BI_DB (10/100 RX ) || || 5 || 1 || tx || 1 || BI_DC || || 5 || 1 || rx || 1 || BI_DD || === P23 Connections (CMS only) || P23 Row || Port || Pair || CMS Function || || 4 || 0 || Tx || LDAQ out 10Gb/s || || 4 || 0 || Rx || LDAQ in 10Gb/s || || 4 || 1 || Tx || Reserved STDIO || || 4 || 1 || Rx || Reserved STDIO || || 3 || 2 || Tx || TCDS2 Out (throttling, TTS+) || || 3 || 2 || Rx || TCDS2 In (timing, TTC+) || || 3 || 3 || Tx || Precision Clock || || 3 || 3 || Rx || LHC Clock || NOTE: "Precision Clock" is reverse direction from standard! This is from [http://ohm.bu.edu/~hazen/CMS/InnerTracker/jhegeman_006_temp.pdf this draft] of the document "CMS ATCA Crate Specification and Hub- and Node Board Requirements" === Possible Mezz-Blade Connectors * Samtec ET60T/ET60S (60A power, up to 24 low-speed signals) * Samtec ERF8/ERM8 (edge-rate diff pair up to 58Gbps) Meetings: * https://indico.cern.ch/event/738681/ (2018-06-20) '''2018-05-31''' Thinking about a common blade for ATLAS L0MDT and CMS IT-DTC. \\ Issues with the current ATLAS design: * FMC stacking height at 8.5mm is too high Issues with the current CMS design (Cornell one): * Really don't like the interposer concept with metal plates, springs etc * Prefer stand-alone mezzanine card operation Plus, there are two different blade designs for no obvious reason. First, looking at low stack height connectors, but not Z-ray. (See Samtec [http://suddendocs.samtec.com/literature/samtec-high-speed-b2b-design-guide.pdf guide]) Samtec families with low stack heights: || '''Family''' || '''Series''' || '''Stack Height''' || '''Notes''' || || Sea-Ray || [https://www.samtec.com/products/lpam LPAM]/[https://www.samtec.com/products/lpaf LPAF] || 4mm || || Edge Rate || [https://www.samtec.com/products/edm6 EDM6]/[https://www.samtec.com/products/edf6 EDF6] || 5mm || || Q Series || [https://www.samtec.com/products/qth QTH]/[https://www.samtec.com/products/qsh QSH] || 5mm? || 28 Gbps+, pairs, power || || || [https://www.samtec.com/products/qte QTE]/[https://www.samtec.com/products/qse QSE] || 5mm || 25A GND plane || || Ultra-Micro || [https://www.samtec.com/products/edm6 EDM6]/[https://www.samtec.com/products/edf6 EDF6] || 5mm || || || [https://www.samtec.com/products/lss LSS]/[https://www.samtec.com/products/lsem LSEM]/[https://www.samtec.com/products/lshm LSHM] || 5mm || || || [https://www.samtec.com/products/st4 ST4]/[https://www.samtec.com/products/ss4 SSR] || 4mm || Below is a figure with dimensions excerpted from the ATCA standard. || [[Image(http://gauss.bu.edu/svn/atlas-phase-2-muon-upgrade/Meetings/2018-05-31_EDF/figs/stack_heights.png)]] || Seems as if we can find a 4mm or 5mm solution. \\ This gives us about 15.7mm above a mezzanine board for components. || Next, thinking about the logic. Is it really that hard to make a common blade? Here are some thoughts: * Build a blade to accommodate 3 mezzanine cards * Plan for only "low speed" mezz-to-mezz communications \\ (SelectIO or < 10Gbps SERDES) * Mezzanine cards would have the optics on board along with DC/DC converters and regulators * Split the CMS IT-DTC into 3 parts * Eliminate the "blade FPGA" from the ATLAS design and designate one mezz card as "master" \\ (this could be a different design). '''ATLAS requirements''' * Sector logic