Version 41 (modified by Eric Hazen, 3 years ago) (diff)


Project APOLLO This is a project to develop a common ATCA blade which can be used for readout and triggering applications in LHC experiments. It is named after the Apollo program CSM spacecraft which separated into Command and Service modules. Photos

Aux boards

Rev A Comments

  • EN_ONE_JTAG_CHAIN should have a pull-up/down and/or jumper so something sensible happens when the IPMC is not installed or programmed.
  • Serial comms between Zynq and CM should be possible without IPMC intervention.
  • How to turn on payload power with no IPMC installed/running?
  • JTAG (and other GPIO) signals must obey ENABLE/READY to avoid driving CM logic when not powered

Reference Material

Consider making mezzanine board 7U high (277.8 mm, see Eurocard info). Depth probably non-standard ~ 200mm as standard depths 160mm and 220mm are not convenient.

P23 Connections (Base ethernet)

P23 Row Port Pair Base Channel Function
6 0 tx 2 BI_DA (10/100 TX )
6 0 rx 2 BI_DB (10/100 RX )
6 1 tx 2 BI_DC
6 1 rx 2 BI_DD
5 0 tx 1 BI_DA (10/100 TX )
5 0 rx 1 BI_DB (10/100 RX )
5 1 tx 1 BI_DC
5 1 rx 1 BI_DD

P23 Connections (CMS only)

P23 Row Port Pair CMS Function
4 0 Tx LDAQ out 10Gb/s
4 0 Rx LDAQ in 10Gb/s
4 1 Tx Reserved STDIO
4 1 Rx Reserved STDIO
3 2 Tx TCDS2 Out (throttling, TTS+)
3 2 Rx TCDS2 In (timing, TTC+)
3 3 Tx Precision Clock
3 3 Rx LHC Clock

NOTE: "Precision Clock" is reverse direction from standard!

This is from this draft of the document "CMS ATCA Crate Specification and Hub- and Node Board Requirements"

Possible Mezz-Blade Connectors

  • Samtec ET60T/ET60S (60A power, up to 24 low-speed signals)
  • Samtec ERF8/ERM8 (edge-rate diff pair up to 58Gbps)



Thinking about a common blade for ATLAS L0MDT and CMS IT-DTC.
Issues with the current ATLAS design:

  • FMC stacking height at 8.5mm is too high

Issues with the current CMS design (Cornell one):

  • Really don't like the interposer concept with metal plates, springs etc
  • Prefer stand-alone mezzanine card operation

Plus, there are two different blade designs for no obvious reason.

First, looking at low stack height connectors, but not Z-ray. (See Samtec guide) Samtec families with low stack heights:

Family Series Stack Height Notes
Sea-Ray LPAM/LPAF 4mm
Edge Rate EDM6/EDF6 5mm
Q Series QTH/QSH 5mm? 28 Gbps+, pairs, power
QTE/QSE 5mm 25A GND plane
Ultra-Micro EDM6/EDF6 5mm
ST4/SSR 4mm

Below is a figure with dimensions excerpted from the ATCA standard. Seems as if we can find a 4mm or 5mm solution.
This gives us about 15.7mm above a mezzanine board for components.

Next, thinking about the logic. Is it really that hard to make a common blade? Here are some thoughts:

  • Build a blade to accommodate 3 mezzanine cards
  • Plan for only "low speed" mezz-to-mezz communications
    (SelectIO or < 10Gbps SERDES)
  • Mezzanine cards would have the optics on board along with DC/DC converters and regulators
  • Split the CMS IT-DTC into 3 parts
  • Eliminate the "blade FPGA" from the ATLAS design and designate one mezz card as "master"
    (this could be a different design).

ATLAS requirements

  • Sector logic

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