Project APOLLO This is a project to develop a common ATCA blade which can be used for readout and triggering applications in LHC experiments. It is named after the Apollo program CSM spacecraft which separated into Command and Service modules. Photos

Debug Log

Aux boards

Rev A Comments

  • EN_ONE_JTAG_CHAIN should have a pull-up/down and/or jumper so something sensible happens when the IPMC is not installed or programmed.
  • Serial comms between Zynq and CM should be possible without IPMC intervention.
  • How to turn on payload power with no IPMC installed/running?
  • JTAG (and other GPIO) signals must obey ENABLE/READY to avoid driving CM logic when not powered

Reference Material

Consider making mezzanine board 7U high (277.8 mm, see Eurocard info). Depth probably non-standard ~ 200mm as standard depths 160mm and 220mm are not convenient.

P23 Connections (Base ethernet)

P23 Row Port Pair Base Channel Function
6 0 tx 2 BI_DA (10/100 TX )
6 0 rx 2 BI_DB (10/100 RX )
6 1 tx 2 BI_DC
6 1 rx 2 BI_DD
5 0 tx 1 BI_DA (10/100 TX )
5 0 rx 1 BI_DB (10/100 RX )
5 1 tx 1 BI_DC
5 1 rx 1 BI_DD

P23 Connections (CMS only)

P23 Row Port Pair CMS Function
4 0 Tx LDAQ out 10Gb/s
4 0 Rx LDAQ in 10Gb/s
4 1 Tx Reserved STDIO
4 1 Rx Reserved STDIO
3 2 Tx TCDS2 Out (throttling, TTS+)
3 2 Rx TCDS2 In (timing, TTC+)
3 3 Tx Precision Clock
3 3 Rx LHC Clock

NOTE: "Precision Clock" is reverse direction from standard!

This is from this draft of the document "CMS ATCA Crate Specification and Hub- and Node Board Requirements"

ApolloHistory -- older stuff

Last modified 4 weeks ago Last modified on May 24, 2019, 12:45:07 PM