The CMS CSC group have asked for some help testing the GBTx interface on their xDCFEB boards, which are due to go into production soon (mid-2018). We held a kick-off meeting on 2018-06-06.

Document SVN: ​http://gauss.bu.edu/svn/cms-csc

Firmware etc: ​http://gauss.bu.edu/svn/cms-csc/XDCFEB_Testing

Wu FC-7 Firmware: ​http://physics.bu.edu/~wusx/download/DCFEB/

Work Log (add new entries at top)

2019-01-25

Wrote control program. SVN: ​http://gauss.bu.edu/svn/cms-csc/Software/xdcfeb-test/trunk/

Check out from SVN. Navigate to trunk directory and source env.sh. Then make. Then bin/xdcfeb. Type "h" for help. As of now the program can run the loop-back test and enter values for the command and control registers. More to come...

Testing status: loop-back to FC-7 works. GBTx doesn't seem to receive the clock (looks intermittent on the XDCFEB test point below the serial number square). The FC-7 shows "LOS" (loss of signal) on it's receiver.

2018-11-02 Getting started

Met briefly with Indara, Ben. Reviewed plan:

• Develop simple FC-7 firmware with circular buffers for Tx and Rx on one GBT link. Include useful status registers and trigger on specific bits/patterns to stop capture.
• Move the VLDB to the CMS lab with USB attachment to one of the CMS machines
• Give Indara an account so she can install the required software

GBTx Output mapping (2X eLink mode)

GBTX DIO	Downlink Frame	Name	Loop-back	FPGA Config
23	79, 78	gbt_sel_gbt_cclk_src	Don't care	0
22	77, 76	gbt_sel_cclk_src	Don't care	1
21	75, 74	gbt_sel_mstr_~slave	Don't care	0
20	73, 72	gbt_sel_8b_16b	0	0
19	71, 70	gbt_sel_gbt_xprm	1	1
18	69, 68	gbta_override	1	1
17	67, 66	gbt_prg_ena	0	1
16	65, 64	!gbt_prg	Don't care	1
15	63, 62	PRG_DATA[15]	Loop data	Configuration data
14	61, 60	PRG_DATA[14]
...	...	...
0	33, 32	PRG_DATA[0]

GBTx Input mapping (2X eLink mode)

GBTX DIN	Rx frame bit
15	63, 62
14	61, 60
13	59, 58
12	57, 56
11	55, 54
10	53, 52
9	51, 50
8	49, 48
7	47, 46
6	45, 44
5	43, 42
4	41, 40
3	39, 38
2	37, 36
1	35, 34
0	33, 32

Draft spec / documentation for FC-7 firmware: DCFEBTestFirmware

2018-09-25 Collecting documentation

• ​Versatile Link project
• ​VLDB Demo Board

Looking at XDCFEB schematic:

• LVDS cable w/ alternate JTAG on page 7
• JTAG on page 10, 11
• Most GBTX and FPGA config interface are on pages 44-45 (last pages).

2018-09-25 meeting notes:

What we need:

• XDCFEB documentation if any
• XDCFEB layout info (just to identify parts, etc). Gerbers would be fine.
• An xDCFEB board plus connectors, etc power supply
• (we have an FC-7)
• FMC mezzanine with high speed SERDES to SFP (commercial, long lead time?)
• Eventually: base firmware for XDCFEB

2018-06-06 meeting notes:

Meeting participants: Indara (BU), Ben Bylsma (OSU), Stan Durkin (OSU), Darien Wood (Northeastern)

Other collaborators: Evaldas Juska and Jason (TAMU), also UCLA, UCSB, UC Davis and others

• DCFEB TWiki page: ​https://twiki.cern.ch/twiki/bin/viewauth/CMS/CSCdescriptionDCFEB
• xDCFEB schematic: ​http://gauss.bu.edu/svn/cms-csc/Docs/xdcfeb_v3a_schematic.pdf
• xDCFEB slides: ​http://gauss.bu.edu/svn/cms-csc/Meetings/2018-06-06/xDCFEB_status5_CMS_Week.pptx

The general plan is to test the production xDCFEB boards at OSU using a VME setup with back-end boards. The xDCFEB has a GBTx ASIC on board which is used to access the configuration interface of the Virtex-6 (XC6VLX130T). They would like us to devise a simple test of this interface. The GBTx has an uplink fiber too but currently it is not foreseen to use this but we should plan to test it as well.

We could write firmware and software for an FC-7 to accomplish this. The bitstream for the XC6VLX130T is 43,719,776 bits, which is larger than the 30Mb or so of block RAM on the 7K420 on the FC-7, but there is a DDR3 on the FC-7 too which could hold the bitstream.