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This page provides implementation details for Prototype II for the designers.

A sine wave with 16-bit precision will be pre-loaded in a 512-word block RAM on the FPGA. A programmable 'phase increment register controls the stimulus frequency. At the maximum 100Hz frequency, the waveform DAC will be updated from the RAM at 51.2kHz. An ADC will measure the current from the reference and active devices alternately at 51.2kHz, providing a new measurement of each at 25.6kHz. This will be accomplished by operating the AD7682 ADC in a mode where it takes samples alternately on two inputs.

As each sample is acquired, it will be multiplied by both the in-phase (sin) and quadrature (cos) values retrieved from the RAM, and the results added to a 24-bit accumulator. Four accumulators are required (reference sin, reference cos, active sin, active cos). Once per stimulus cycle (maximum 100Hz) the four accumulators are zeroed and the four 32-bit values transferred to the microcontroller.

In addition, the raw samples are stored in an additional block ram which may be read by the microcontroller for diagnostic purposes.

PCB Documentation

• Notes • SchematicRevisions



Source Code

Working Code

Working version with one significant known bug in "AC" command (repeats measurements)

Test Versions

The FPGA logic (designed by Bill) will provide the following:

  • Interface to 4-output DC bias DAC
  • Interface to 2-output offset cancel DAC (may be combined with above)
  • Waveform BRAM to hold 256-sample 16-bit sinusoidal waveform
  • Logic to drive an AC DAC from above at a programmable rate (1-100Hz waveform rate, 256Hz-25.6kHz sample rate)
  • Logic to read out at the same sample rate one multiplexed ADC reading the AC current waveform(s) measured on the samples. The ADC will provide one or two 16-bit samples (reference and active separately, or the difference). The ADC outputs will go to two destinations:
    • 1. Multiply/accumulate logic which will multiply the samples by the sin and cos outputs from the waveform generator and accumulate a 24-bit sum. There will be a total of 4 such sums (Active sin, active cos, reference sin, reference cos) produced once per cycle and made available to the PicoBlaze?
    • 2. A block ram which can hold one complete waveform (256 samples) of 2x16 bits each.
  • A control register with bits for gain select, multiplexer settings and mode selects
  • A status register of some sort

The PicoBlaze? interface will be bus-oriented, as described here: BioDelayGenerator except that the address will be expanded to 7 bits.

PCB Components

  • DAC7564
  • DAC7551
  • TLV5638
  • AD7682
  • 8 current-sensitive amplifiers with switchable 10x gain (wired to 4 inputs each on the ADCs)
  • 8 100x gain voltage amplifiers with offset cancel input from DAC
  • A Spartan-3AN FPGA (probably an XC3S50AN-TQ144).
  • An RS-232 interface
  • A crystal oscillator (50MHz?)
  • Voltage regulators to power everything from +4.5, -4.5V from batteries or external power
  • LEDs / buttons
  • Connectors:
    • Carrier PCB (two 12-pin headers)
    • DB-9 for RS-232
    • 2mm round coax jack (or similar) for external power
    • 4-pin Molex for battery power
    • Auxiliary connector (for i.e. LCD character display)

LCD Display

An LCD display may be added. We have a Digilent PMOD-CLP (data sheet). This uses the KS0066 controller from Samsung (data sheet) operating in 4-bit mode is available here

Last modified 5 years ago Last modified on Nov 8, 2013, 10:17:54 AM