wiki:AtlasMezzTesting

This page has some ideas for a modern mezzanine board tester to support production of spares and long-term maintenance of the ATLAS MDT on-chamber electronics.

Resources

Instructions for Use

Set up and install software

  1. Install gcc
  2. Install Python 2.7
    1. Install numpy, scipy, and matplotlib (can install individually, or with  Anaconda 2.7 (recommended))
  3. run "svn co  http://gauss.bu.edu/svn/atlas-mezz-tester.hw/tags/v001/Software/"
  4. Go to Software/cli and run make to build the software
  5. Make sure the user has access to USB devices

User instructions

Full user manual located at:  http://gauss.bu.edu/svn/atlas-mezz-tester/Documentation/User_Manual/mezzCardTesterUserManual.pdf

  1. Insert an MDT card in the tester
    1. Ensure the tester is switched off.
    2. Remove previous card if it is present by carefully pulling up around the headers.
    3. Line up the headers and firmly press down on card.
    4. Take care not to flex the card or the Mezz Tester PCB while removing or installing.
    5. Turn on tester.
    6. (if needed, cd ../tester)
  2. Run the "MezzTester.py" script.
    1. The default device is '/dev/ttyUSB0'. An alternate may be specified with the -D flag. ex. './MezzTester.py -D /dev/ttyUSB1'
  3. Enter name and location to be logged in the database.
  4. Let the scan run. It will output progress so you know it is running.
  5. When it is done, it will tell if and what tests failed.
  6. At the comment prompt, enter any comments you would like stored with the test, or just press enter for none.
  7. Generate plots of the data if desired. (You can enter to skip).
  8. Repeat steps 4-8 as needed.
  9. type "q" to quit at any of the ID prompts.

Project History

Prototype I

The first prototype of the hardware will be based on a Xilinx evaluation board with an adapter card designed by me (Hazen). Documentation:

Revision A

The first revision of the hardware moved the FPGA, pulse injector, and card header on a single board designed by Dean De Carli. This board was manufactured in July 2014 and is the "final" version.

Revision B To Do

The first revision of the hardware moved the FPGA, pulse injector, and card header on a single board designed by Dean De Carli.

  • Add the 390 ohm termination resistors.
  • External pulse injector
    • Use a new DAC that properly functions in the given voltage range
      • The original DAC was the LTC2635m, which was used on the prototype. There was a snafu with the assembly house in which they said they couldn't solder the part with leaded
        solder because it had a pad underneath the chip that was tinned with unleaded solder. The part was swapped out for the AD5625. This limitation ended up being an artificial one,
        and the boars were assembled with leaded solder anyway, but by the time they agreed to use leaded solder, the board and the gerbers were already altered.
    • Also adjust pulse injection resistor divider for a greater pulse height
    • Alternatively, one could look into connecting the existing DAC to 5V (not recommended)
    • This will require re-tuning of the DAC sweep tests. The Python verification routine and test parameters will need adjusted, and I suspect some of bounds programmed into the MezzTool? will adjusted as well.

Software from original tester

Due to the DAQ rate limitations of the TDC and difficulty locating the sources of the original tester, we have experienced difficulties recreating the original results of the ASD tester. Besides the obvious plateau in center of the data from the TDC pegging out, the data appears to be acceptable. Fortunately, we were able to locate a cd with the source of the original tester at the EDF. The image can be  downloaded from here:.

Observations:

  • For the noise test, the ASD hysteresis register setting is set to 0 in the original tester, while the new tester has been setting it to 4.
  • I have been doing a non-linear least squares fit of the Gaussian equation listed in the ASD manual. The original tester takes the log of the y-values and does a least-squares quadratic fit on the data,

and then from A*x2 + B*x + C, uses A, B, C as Voff, Sigma,and Rate, respectively.

Changes made to hardware/software on September 14, 2015

  • Added 390 termination resistors on all the channels
  • Adding the termination resistors forced a change in the dac sweep fit parameters:
    • Increased slope range to 15 to 19.5.
    • Decreased ASD threshold step size
  • Corrected the offset spread test to compare the channels on each individual chip, not the entire card.
  • Set ASD hysteresis to 0 for threshold sweep test.

Design Ideas

Meetings

Mezz card connector signals from  the schematic

'Pin(s) Name Comments
1,3,5,7 AVdd_In Power supply ~5V
2,4,6,8 AGND Analog GND
9,10 Test in LVDS test pulse
11,12 Temp_Sense TMP32 temp sensor output (voltage)
13,14 AVdd_Sense AVdd output for sensing
15,16 DVdd_Sense DVdd output for sensing
17,19,21,38,40 DVdd_IN Power supply 2 ~5V
18,20,22,24,34,36 DGND Digital GND
23 nRESET AMT Reset
25,26 SERDAT LVDS output data 40/80 MB/s
27,28 CLK LVDS clock in 40/80 MHz
29,30 ENC Encoded control in 40/80 MB/s
31,32 STROBE LVDS output strobe
33,35,37,39 JTAG AMT JTAG signals (TCK,TDI,TMS,TDO)

All required hardware interface functions could be provided by a rather simple PCB with a modern FPGA and a few DAC and ADC channels.