wiki:AtlasL0MDTPrototypeNotes

Notes from CERN meeting January 29, 30 2018

Slides from Meeting

Current thinking is:

  • Input FPGA (7 series or Ultrascale) with all MDT links, SL inputs, DAQ outputs
    • GBT-FPGA receive/decode
    • SL receive/process
    • hit extractor
    • DAQ functions
    • Maybe DDRx SDRAM
  • "Virtual Daughterboard" FPGA (Zynq) with SL outputs
    • Segment finder
    • Track fitter
  • Control FPGA with Linux (likely a mezzanine e.g. Enclustra Mars)
  • Chip-to-chip links
    • ~20 SelectIO plus serdes
    • Could be AXI chip-to-chip or simple custom link
  • CERN IPMC

Prototype could just have two copper Ethernet ports to IPMC, control Zync

Prototype link counting (board, bare minimum):

Target Tx Rx Notes
MDT CSM 3 6 2 MDT chambers
SL 4 4 2 SL boards
Ethernet 1 1 Maybe XAUI or?
FELIX 2 1
Total 10 12

Input FPGA thoughts

Minimum size part KU040 (20 SERDES) maybe A1156 pkg

Should be upward-compatible footprint in case KU040 resources inadequate

"Virtual Daughterboard" FPGA thoughts

Some conflicting requirements here:

  • For FPGA Legendre, would like ~600k FFs, LUTs
  • For Zynq algorithm, would like 7045 or 7100 Zynq for compatibility (but largest 7100 has "only" 277k LUTs, only enough for one Legendre engine)

Possibly an FMC mezzanine even here?

Control FPGA

  • E.g. 7010/7020
  • System control only
  • Enclustra or PicoZED module?
Last modified 5 years ago Last modified on Feb 1, 2018, 11:47:21 AM