ATLAS Chip and Mezz Card testing

This page is created in 2018 to provide a summary of available documentation on various ASD chip and mezzanine card test hardware.

Chip Tester (ca 2001)

This was a joint effort between Harvard and BU. There are two PC board designs.

The main board (documentation below) contained all the mixed-signal circuitry to provide bias to the chip, input stimulus and readout the results. It includes an FPGA which implemented much of the control functionality and a simple TDC to digitize the ASD output. It communicated through a large cable with a National Instruments parallel interface board in a PC. Unfortunately most of the firmware and software source code has been lost in time.

The second board with a clamshell socket was a passive board which provided connections to the main board. Unfortunately all documentation for this board has been lost, although we have two of them with clamshell sockets at BU. Here are two photos of this board.

Mezzanine Board Tester (ca 2014)

This is a new development at BU. It consists of a single board with FPGA and all required mixed-signal circuitry to test a mezzanine board of any of the four standard 3 or 4-layer types.

Full documentation is here: AtlasMezzTesting (if a bit disorganized)

Some missing files can be found here:

It was anticipated to make a special mezzanine board version with a clamshell socket to implement a new chip tester. This would still be possible but has not been done at BU.


(duplicated from AtlasMezzTesting page for convenience)

Last modified 4 years ago Last modified on May 7, 2019, 1:17:40 PM