wiki:500MSPS_Prototype

This page describes a possible prototype using the new ADS5463 FADC operating at (up to) 500MSPS. Back to Fast_WFDs

'Clocking

The clock input is differential, with self-biasing DC levels. Best driven with 50% duty cycle, AC-coupled differential input.

Options:

  • 1GHz sine wave on-board oscillator, PECL divide-by-two
  • External 500MHz or 1GHz sine wave input
  • PLL frequency multiplier from (i.e.) 10MHz reference input

12 wks lead time

  • Crystek CVCS0-914 1GHz SAW. ~$115 at Digi-Key. Sine output.

'Analog Input

The THS4509 looks like a good bet.

Last modified 6 years ago Last modified on Nov 8, 2013, 10:17:53 AM